Charge transfer readout circuits
AssigneeRCA Corporation
InventorPaul Kessler Weimer
Life of this patent
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Abstract
During readout, the signals induced on the columns of a charge transfer array cause currents to flow through respective conduction paths of field effect transistors connected to the columns. The threshold voltage V.sub.th of each transistor is compensated for prior to readout by establishing the gate electrode thereof at a quiescent gate bias level V.sub.c +V.sub.th, where V.sub.c is the quiescent voltage at the source electrode of that transistor. The effects of dark current or other fixed signal level it is desired to discriminate against associated with the respective columns of the array, also may be compensated for by reducing the quiescent bias level on the gate electrode by an amount proportional thereto.
Claims20
In combination:
- a field effect transistor having source, drain and gate electrodes, said drain electrode coupled to a circuit point which can be electrically floated;
- means coupled to said source electrode for placing the same at a reference voltage level (V.sub.c);
- means ac coupled to said gate electrode for inducing thereon a potential greater than one threshold voltage (V.sub.th) above V.sub.c, in the forward direction;
- means providing a low impedance dc path between said gate and drain electrodes during the time said induced potential is present at said gate electrode and while said drain electrode is electrically floating, whereby charge carriers are conducted through the source-to-drain electrode path of said transistor until the voltage difference between said source and gate electrodes reduces to a value substantially equal to V.sub.th, whereupon conduction ceases through said source-to-drain electrode path;
- and
- means for opening said dc path while said voltage difference between said source and gate electrodes is substantially equal to V.sub.th, whereby a quiescent forward bias V.sub.th is established between said source and gate electrodes.
The combination of:
- a charge transfer array having a plurality of columns;
- an output register having at least the same number of stages as there are columns;
- a circuit for coupling each column to a different register stage for permitting the transfer, in parallel, of a row of signals from the charge transfer array to the output register, said circuit including a plurality of transistor circuits, one per column, each such circuit comprising:
- a field effect transistor having source, drain and gate electrodes;
- means coupled to said source electrode for placing the same at a reference voltage level V.sub.c ;
- means connecting the drain and gate electrodes to one another via a low impedance path and for ac coupling a potential to said gate electrode at a level such that current flows through the source-to-drain path of said transistor until a quiescent bias level V.sub.c +V.sub.th is established on said gate electrode, whereupon current flow ceases through said transistor, where V.sub.th is the threshold voltage of said transistor;
- means for then disconnecting said drain electrode from said gate electrode;
- means for supplying a signal from a column between said source and gate electrodes of said transistor after said quiescent bias level has been established;
- and
- means for connecting said drain electrode to a stage of said register for transferring any signal produced at said drain electrode in response to current flow through said source-to-drain path, to said stage.
Dependencies are inferred from the claim text.