Phase locked loop for synchronizing VCO with digital data pulses

In a phase-locked loop, a phase comparator capable of providing phase error magnitude and direction information for synchronizing a voltage controlled oscillator with a data pulse train which consists of pulses spaced apart in integral multiples of a fundamental clock period comprising

• oscillatory means controlled in period by a phase error signal for producing output pulses of the prime period of said data pulses in the absence of any phase error, of greater period in the presence of a phase error of a given polarity, and of lesser period in the presence of a phase error of opposite polarity,
• bistable means connected to receive said output pulses and train of data pulses at separate input terminals for producing complementary pulses at Q and Q output terminals thereof in response to being set at the end of each cycle of said oscillatory means while a data pulse is present and to being held clear whenever a data pulse is not present,
• first coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said Q output terminal of said bistable means for gating a pulse out while both input terminals thereof receive a binary signal of predetermined level,
• second coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said Q output terminal of said bistable means for gating a pulse out while both input terminals thereof receive a binary signal of said predetermined level, and
• means for producing said phase error signal directly proportional to the difference in the pulse widths of pulses gated out by said first and second coincidence gating means with a given polarity when pulses from said first gating means are greater, and of opposite polarity when pulses from said second gating means are greater.

A phase-locked loop employed to synchronize a voltage controlled oscillator with a data pulse train, where said data pulse train is comprised of pulses spaced apart in integral multiples of a fundamental clock period comprising

• a flip-flop having true and complementary output terminals, and having a first input terminal adapted to place said flip-flop in a first state with said true output terminal at a predetermined high voltage level and said complementary output terminal at a predetermined low voltage level in response to the end of a cycle of said oscillator in the presence of a data pulse, and having a second input terminal adapted to place said bistable means in a second state with said true output terminal at said low voltage level and said complementary output terminal at said high voltage level in response to the absence of a data pulse,
• first coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said true output terminal of said flip-flop for gating a pulse out while both input terminals receive a voltage signal at one of said predetermined levels,
• second coincidence gating means having two input terminals, one connected to said train of data pulses and the other to said complementary output terminal of said bistable means for gating a pulse out while both input terminals receive a voltage signal at said one predetermined level,
• means for producing said phase error signal directly proportional to the difference in the pulse widths of pulses gated out by said first and second coincidence gating means with a given polarity when pulses from said first gating means are greater in width, and of opposite polarity when pulses from said second gating means are greater in width, and
• means for applying said phase error signal to said voltage controlled oscillator to control the frequency thereof.