Method of making N-channel MOS integrated circuits

A method of making N-channel, silicon-gate MOS integrated circuit devices of the type having memory cells therein, comprising the steps of:

• growing a thin uniform silicon oxide coating over an entire surface of a monocrystalline silicon slice;
• covering the thin silicon oxide coating with a thin uniform layer of silicon nitride;
• removing the silicon nitride coating in a pattern to expose selected areas of the thin silicon oxide coating;
• implanting a first conductivity-type determining impurity into shallow surface-adjacent regions of the silicon in said selected areas by exposing the slice to an ion beam, such implanting being done through said thin silicon oxide coating;
• subjecting the slice to an elevated temperature of at least about 1000.degree. C for at least about 1/2 hour in an inert atmosphere to reduce the damage to the crystalline structure of the silicon beneath said exposed selected areas caused by the ion beam and to raise the concentration of the first impurity in the silicon below said surface-adjacent regions;
• oxidizing the slice at a temperature below said elevated temperature for a time greatly exceeding that used in the prior step to create a thick silicon oxide coating in said exposed selected areas;
• removing the remaining silicon nitride from the surface of the slice;
• and
• forming MOS transistors and oxide-dielectric capacitors for said memory cells on said slice by diffusing or implanting into the slice second conductivity-type determining impurity of opposite type from the first impurity, the regions in the slice created by the first impurity being contiguous to that formed by the second impurity at least in the areas substantially surrounding the capacitors.