High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
AssigneeInternational Business Machines Corporation
InventorsIrving T. Ho, Jacob Riseman
Life of this patent
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Abstract
An improved FET structure and method of making same is disclosed. The gate structure of the FET includes a phospho-silicate glass as the insulator and polysilicon as the gate conductor. A thin layer of silicon nitride is formed over the polysilicon and selectively etched so as to remain only over gate areas and other areas where it is desired to extend the polysilicon as a conductor. The unmasked polysilicon is oxidized to form the thick oxide surface coating. The disclosure also describes the use of oxide rings and epitaxial layers to reduce parasitic effects between adjacent FET devices in an integrated circuit.
Claims4
A method of fabricating a field effect transistor comprising the steps of:
- a. forming a thin layer of oxide on a wafer of monocrystalline silicon,
- b. depositing a layer of conductive polycrystalline silicon on said thin layer of oxide,
- c. forming a layer of silicon nitride on said polycrystalline layer,
- d. within at least the area of said wafer where said field effect transistor is to be fabricated, removing portions of said silicon nitride layer to form a silicon nitride mask over said polysilicon layer, said mask in said area covering only the region to be the gate structure of said field effect transistor,
- e. oxidizing all said polysilicon layer not covered by said silicon nitride mask to form a thick oxide layer thicker than said polysilicon layer,
- f. opening holes within said thick oxide layer on opposite sides of said gate structure,
- g. introducing impurities into the surface of said monocrystalline silicon layer exposed by said openings to form the drain and source regions of said field effect transistor, and
- h. forming conductive contacts to said source and drain regions.
A method of fabricating a field effect transistor comprising the steps of:
- a. forming a thin layer of oxide on a wafer of monocrystalline silicon,
- b. depositing a layer of conductive polycrystalline silicon on said thin layer of oxide,
- c. forming a layer of silicon nitride on said polycrystalline layer,
- d. within at least the area of said wafer where said field effect transistor is to be fabricated, removing portions of said silicon nitride layer to form a silicon nitride mas over said polysilicon layer, said mask in said area covering only the region to be the gate structure of said field effect transistor,
- e. oxidizing all said polysilicon layer not covered by said silicon nitride mask to form a thick oxide layer thicker than said polysilicon layer,
- g. opening holes within said thick oxide layer on opposite side of said gate structure, and,
- g. introducing imputirites into the surface of said monocrystalline silicon layer exposed by said openings.
Dependencies are inferred from the claim text.