US 4,054,950 AGranted

Apparatus for detecting a preamble in a bi-phase data recovery system

AssigneeNCR Corporation

InventorJames G. Boone

Life of this patent

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Abstract

In order to detect the eminent reception of a valid bit serial message, a preamble constituting a string of predetermined number of clock pulses only is employed. Prior to detection of the preamble, each clock and data pulse from the raw data stream is applied to the increment input of a resettable counter. Each clock pulse is also used to trigger a monostable multivibrator which issues a pulse approximating three-fourths of a cell period. This pulse is ANDed with the next subsequent data period, and if a data "1" bit is detected, the satisfied condition is used to reset the counter. Thus, the counter can only reach a terminal count if a valid preamble is received. When the counter attains its terminal count, a latch flip-flop is set and a resultant "separation enable" signal issues to activate straightforward logic for separating the incoming clock and data pulses. Setting the latch also disables the preamble detection logic until an "end of data field" code is sensed whereupon the counter and latch are both reset to resume observation of the raw data stream for a preamble.

Claims4

Dependent claims

Apparatus for detecting an all clock pulse preamble to an encoded digital message having clock pulse and data pulse components, comprising:

A. a counter having an input adapted to receive said encoded digital message and to increment in response to pulses, a reset input, and an output for issuing an output signal when said counter reaches a predetermined count, said predetermined count corresponding to the number of clock pulses contained in the clock pulse preamble of said encoded digital message;
B. bistable latch means having a first input coupled to said counter output and responsive to an output signal therefrom to assume a first state indicating receipt of a clock pulse preamble, said bistable latch means having a second input responsive to a signal applied thereto for assuming a second state indicating non-receipt of a clock pulse preamble;
C. gate means operatively connected to said bistable latch means for providing an output pulse when said bistable latch means is in said second state and a pulse is received from said encoded digital message;
D. monostable means having an input and an output, said monostable means issuing an output pulse having a predetermined time duration in response to an input pulse applied thereto from said gate means, said predetermined time duration being less than the time period between successive clock pulses;
and
E. reset means coupled to said counter and responsive to the simultaneous occurrence of an output pulse from said monostable means and a data pulse from said encoded digital message for resetting said counter prior to said counter reaching said predetermined count.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 05/681,674Filed 29 Apr 1976
Granted: 18 Oct 1977
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11B 20/12
Digital recording or reproducing: formatting, e.g. arrangement of data block or words on the record carriers
G11B 27/3027
On the same track as the main recording: used signal is digitally coded
H04L 7/046
Using special codes as synchronising signal: using a dotting sequence
H04L 7/033
Speed or phase control by the received code signals, the signals containing no special synchronisation information: using the transitions of the…