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US 4,054,921 AGranted
Automatic time-base error correction system
AssigneeSony Corporation
InventorMitsushige Tatami
Life of this patent
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Abstract
An automatic time-base error correction system having a pair of random access memories, in which an input signal including timing errors is written in one of the random access memories alternatively at a rate corresponding to the timing errors, and an output signal is alternatively read out from the memories at the constant rate.
Claims7
An automatic time-base error correction system comprising:
- a. means for providing an input analog signal and a pilot signal having the same time-base errors;
- b. random access memory means;
- c. read-in addressing means for generating a read-in address signal for said random access memory means having a variable rate in accordance with the rate of said pilot signal;
- d. means for digitalizing the input analog signal at a time specified by said pilot signal;
- e. means for coupling the digitalized signal to a data port of one of said random access memory means as well as means for applying said read-in address signal from one of said read-in addressing means to an address port of said one random access memory means;
- f. read-out clock means for generating read-out clock pulses;
- g. read-out addressing means for generating a read-out address signal having a rate in accordance with said read-out clock means;
- h. means for applying said read-out address signal to an address port of another of said random access memory means as well as means for applying said read-out clock means to said another random access memory means to cause data at a specified location to be read-out said another random access memory means;
- i. means for converting the output of said another random access memory means into analog form;
- j. control means for selecting one of said read-in addressing means to generate read-in addresses for said one of said random access memory means having further means operable to control when said read-out addressing means generates read-out addressess for said another random access memory means;
- and
- k. means to detect when said another random access memory means has had all data read-out and means to interchange read-in, read-out functions of said one random access memory means and said another random access memory means at that time.
9 more elements
Dependencies are inferred from the claim text.