Device for forming channels

In a device for forming channels comprising H detectors regularly spaced out on a circular base;

• H peak limiters, each peak limiter being connected to the output of a detector;
• and a chain constituted by an alternate sequence of adders having several inputs and of delay devices, each delay device comprising several elementary delay cells .tau.(.tau.=1/F.sub.H (F.sub.H being a clock frequency applied to the delay devices) and being connected at their output to an input of an adder of the chain;
• the improvement comprising:
• means for sampling at a frequency F.sub.V signals coming from the H peak limiters, where F.sub.V =.sup.F H /H(k), k being a sub-multiple of H;
• a square matrix of k .times. k shift registers, each of these registers comprising H/k stages, the k registers of each line of the matrix being connected in series and the series output of the first being connected to the input of the last register to form a closed loop circuit, the H/k parallel outputs of each register of a column of the matrix being connected to the H/kparallel inputs of the following register of the said column, some parallel outputs of the k .times. k registers of the matrix being applied to the inputs of the adders of the chain;
• means for transferring the data coming from the sampling means towards the first line of the square matrix which shift by H/k (modulo H) the numbers of the peak limiters transferred once every 1/F.sub.V ;
• and
• a clock supplying a frequency F.sub.H used for controlling the movement of the data in the lines of the matrix and in the delay devices and a frequency F.sub.V used for controlling the sampling means and the transfer means as well as the advance of the data along the columns of the matrix.

In a device for forming channels comprising H detectors regularly spaced out on a circular base;

• H peak limiters, each peak limiter being connected to the output of a detector;
• and a chain constituted by an alternate sequence of adders and of delay devices, each delay device comprising several elementary cells .tau.(.tau.=1/F.sub.H F.sub.H being a clock frequency applied to the delay devices) and being connected at their output to an input of an adder of the chain, the improvement comprising:
• means for sampling at a frequency F.sub.V =.sup.F H/H(K) (k being a sub-multiple of H greater than unity), signals coming from the H peak limiters;
• h main shift registers (h<
• k) forming an open loop circuit, each of these registers comprising H/kstates;
• means for transferring the data coming from the sampling means towards the main registers which shift by H/k(modulo H), the numbers of the peak limiters transferred once every 1/F.sub.V ;
• i charging shift registers whose input is connected to the output of i registers taken from among the k main registers (i<h), each of the said charging registers comprising H.multidot.(k -l) /k stages;
• and
• a clock supplying a frequency F.sub.H used for controlling the shifting of the data along the open loop cntstitued by the h main registers and along the charging registers as well as in the delay devices and a frequency F.sub.V used for controlling the sampling means and the transfer means, some parallel outputs of the i charging registers and of the main registers to which they are connected being connected to inputs of the adders of the chain and in that the delay devices comprise the same number qH of elementary cells where q .gtoreq.1.

A device for determining the direction of propagation of signals detected by an array of H signal detectors regularly spaced on a circular base line by accumulating signals derived from an incident wave travelling in a predetermined direction past the array of signal detectors and by scanning through a plurality of predetermined directions, the device comprising:

• a plurality of device input terminals for receiving signals from the H detectors,
• a source of sampling signals having a frequency F.sub.V,
• shift register means having parallel inputs connected to the device inputs and controlled by the sampling signals to parallel load signal samples at sampling instants once every sampling period,
• a chain comprising an alternating sequence of adders and delay devices in which each delay device has a series input connected to the output of the preceding adder and a series output connected to one of the inputs of the succeeding adder and in which the output of the last adder of the chain provides an output signal for the device as a whole,
• each adder having a set of inputs connected to a pattern of parallel outputs of said shift register means, said pattern correspondng to the pattern of signal detectors which detect the same incident wave during one sampling period provided said incident wave is travelling along said predetermined direction,
• each of said delay devices having a delay period chosen to so delay the output of its input adder that the sun derived by said input adder during one sampling period from said incident signal and any possible previous sum is added by the output adder of said delay device with the signals derived from said incident signal during a subsequent sampling period, whereby signals derived from said incident wave during a plurality of sampling periods are accumulated by said chain, and
• a source of scanning signals having a frequency F.sub.H, where F.sub.H is higher than F.sub.V, connected to said shift register means to cause the signal samples stored therein to shift past said parallel outputs to said adders whereby a plurality of different directions are scanned by said device by effectively rotating the connections between the shift register means and the device input terminals.