Sense latch circuit for a bisectional memory array
AssigneeNippon Electric Co., Ltd.
InventorHajime Shirato
Life of this patent
Estimating the term…
Abstract
A memory circuit includes a plurality of memory cells arranged in an array of intersecting rows and columns and a plurality of differential amplifiers corresponding to the number of columns in the array. The memory array is divided into first and second row groups. Each of the differential amplifiers has one input connected to the memory cells in one of the row groups in one of the columns, and a second input connected to the memory cells in the second row group and to the same column connected to the first input. An output sense amplifier has one input selectively connected to the first input of a selected differential amplifier, and a second input selectively connected to a second input of the selected differential amplifier.
Claims8
A memory circuit comprising a plurality of memory cells arranged in an array of rows and columns, said memory cells each consisting of a single field effect transistor and a storage capacitor, said memory array being divided into first and second row groups;
- a plurality of cross-coupled differential amplifiers having first input terminals respectively connected to the memory cells belonging to said first row group and each column, and second input terminals respectively connected to the memory cells belonging to said second row group and each same column as that connected to said first terminal;
- and output sense amplifier having first and second input terminals;
- first means for operatively connecting the first terminal of a selected one of said differential amplifiers to said first terminal of said sense amplifier, and second means for operatively connecting the second terminal of said selected differential amplifier to said second terminal of said sense amplifier.
A memory circuit comprising a plurality of memory cells arranged in an array of rows and columns, said array being divided into first and second row groups;
- a plurality of differential amplifiers having first input terminals respectively connected to the memory cells belonging to said first row group and each of said columns, and second input terminals respectively connected to the memory cells belonging to said second row group and each same column as that connected to said first input terminals;
- first and second input-output bus lines;
- first means for operatively connecting the first terminal of the selected differential amplifier to said first input-output bus line;
- second means for operatively connecting the second terminal of said selected differential amplifier to said second input-output bus line;
- and means for simultaneously supplying said first input-output bus line with one of the logic "1" and "0" signals and said second input-output bus line with the other of said logic "1" and "0" signals when said memory circuit is enabled in the write-operation mode.
Dependencies are inferred from the claim text.