Channel gain imbalance compensation for FSK demodulator
AssigneeRockwell International Corporation
InventorWilliam S. Elliott
Life of this patent
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Abstract
Channel gain imbalance in a FSK demodulator for receiving binary data is ameliorated by developing D. C. compensating signals indicative of the imbalance through the energy contained within a predetermined bandwidth of the demodulation channel pair output signals and arithmetically combining them with the channel output signals to counteract the imbalance bias contained therein.
Claims11
In combination with an FSK demodulator having a pair of bandwidth limited channels formed with a pair of envelope detectors for providing D.C. output signals indicative of binary data and an arithmetic means for arithmetically combining the detector output signals to replicate the transmitted data bit stream, a gain imbalance compensating means, comprising:
- a pair of compensating circuits, each being connected to the output of a different one of the pair of detectors for providing a D.C. compensating signal proportional to the energy contained within a predetermined bandwidth of its associated detector output signal, and
- means for applying the compensating signals to the arithmetic means such that each counteracts its associated detector output applied thereto.
A method of providing gain imbalance compensation in an FSK demodulator having a pair of bandwidth limited channels formed with a pair of envelope detectors for providing D.C. output signals indicative of binary data and an arithmetic means for arithmetically combining the detector output signals to replicate the transmitted data bit stream, comprising:
- generating a pair of D.C. compensating signals, each being proportional to the energy contained within a predetermined bandwidth of a different one of the detector output signals, and
- applying said compensating signals to the arithmetic means such that each counteracts its associated detector output applied thereto.
A FSK demodulator for replicating a binary data bit stream from a FSK signal, comprising:
- a pair of mark and space channels, each having a serially connected bandpass filter and envelope detector for receiving the FSK signal and providing at the detector output a D.C. signal whenever a received bit conforms to its associated binary state;
- arithmetic means for arithmetically combining the outputs of said channel detectors to replicate the transmitted data bit stream;
- a pair of compensating circuits, each being connected to the output of a different one of said channel detectors and including a serially connected bandpass filter and envelope detector for providing at the output of said detector a D.C. compensating signal proportional to the energy contained within a predetermined bandwidth of its associated detector output signal, and
- means for applying the compensating signals to the arithmetic means such that each counteracts its associated detector output applied thereto.
Dependencies are inferred from the claim text.