Balanced synchronous detector circuit

A balanced synchronous detector circuit for detecting the amplitude of a received signal and for detecting the phase difference between said received signal and a generated signal, comprising:

• a first double-balanced modulator having a first section provided with a first set of input terminals to which said received signal is applied and a second section provided with a second set of input terminals to which said generated signal is applied, said second section being provided with a set of output terminals;
• a second double-balanced modulator having a first section formed of a portion of said second section of said first double-balanced modulator and a second section provided with a set of input terminals to which a signal whose frequency is an integral multiple of the frequency of said generated signal is applied, said second section of said second double-balanced modulator being provided with a set of output terminals;
• means coupled to said set of output terminals of said first double-balanced modulator to provide a signal proportional to the phase difference between said received signal and said generated signal applied to said first and second sets of input terminals, respectively, of said first double-balanced modulator;
• and
• means coupled to said set of output terminals of said second doubled-balanced modulator to provide a signal proportional to the amplitude of said received signal applied to said first set of input terminals of said first double-balanced modulator.