US 4,054,747 A · Data buffer

Abstract

A data buffer makes use of a plurality of buffer storage cells into which serial bit streams are sequentially written, in order to obtain correction for phase jitter. A write clock signal is derived from the serial bit stream and is used to sequentially write the digits into the cells. A stable clock source is used to provide the basic timing for sequentially reading the bits out from the buffer storage cells, and a logic circuit is used in conjunction therewith to obtain the retimed serial bit stream. The write and read timing signals should have a maximum time separation to allow for maximum correction of phase jitter, and it is critical that the write and read signals should alternate. A monitor and reset circuit compares a selected write signal with a selected read signal and, where a violation of the alternating write-read condition occurs, the circuit resets the write timing and holds it until the read timing has attained a particular state.

Claims9

Dependent claims

Apparatus for retiming a serial bit stream which comprises:

a first timing means providing N sequentially timed outputs, each at a rate which is 1/N.sup.th that of the bit rate of said serial bit stream,
means for sequentially storing N binary digits, each said digit being written into said storing means by one of said N timed outputs from the first timing means;
a second timing means including a clock means having an output which provides a clock rate at substantially the bit rate of said serial bit stream and having N sequentially timed outputs, each at a rate which is 1/N.sup.th of said clock rate;
logic means responsive to said second timing means for sequentially reading out the binary digits from said storage means;
and
monitoring means having one input connected to monitor one of the N sequential timed outputs of said first timing means, having second and third inputs connected to monitor two of the N timed outputs of said second timing means to determine if the write-read inputs alternate and to provide an output signal which resets the N sequential outputs of one said timing means in the event the write-read sequence does not alternate.

3 more elements

Dependencies are inferred from the claim text.

Data buffer

Life of this patent

Data buffer

Life of this patent

Abstract

Claims9