Read and write circuitry

#The present invention relates to circuitry providing both read and write capability for a two track card reader magnetic head which senses flux changes in either track. The read electronics is composed of an analog section and a F/2F to serial decoder. The analog section begins by amplifying the read head output data from a magnetically encoded card being read. The amplified signal is supplied to symmetrical and complimentary amplifiers which produce only positive outgoing signals regardless of the polarities in the flux reversals occurring at the read head. The signals are peak detected and made compatible with positive TTL logic. The digital section separates the clock pulses and the data pulses for transmission to a decoder whose bit cell timing reference is selectively altered by adjusting the RC constant of the timer.

#The write electronics interfaces TTL logic input and the current drive used for writing with the magnetic read head channels. The electronics further provides a control and level shifting network so that the magnetic head is used for both reading and writing. Positive NOR gating is used in the write electronics to supply the current drive from positive 12 volts to ground or from ground to negative 12 volts through a pair of switching transistors, only one of which is conductive at any given time. The read circuitry, also connected to the magnetic read head, meanwhile is isolated from the 12 volt write signal by a high impedance supplied by clamping rectifiers of a differential amplifier which interfaces the read head with the read electronics. Similarly rectifiers interface the write circuitry with the read head and are high impedance at the operating voltages of the read electronics. Thus the high impedances respectively in the read and write circuits isolate one from the other.

#It is accordingly an object of the present invention to provide both read and write capability in the same magnetic head of a card reader device.

#FIGS. 1a, 1b, and 1c are composite schematic diagrams of the read electronics according to the present invention.

#FIG. 2 is a chart of the integrated circuit components used in the present invention.

#FIGS. 3a and 3b are composite schematic diagrams of the write circuitry according to the present invention.

#With more particular reference to FIGS. 1a-1c in the drawings there is shown generally all 1 a read circuit according to the present invention. The read head includes two tracks inductively coupled at terminals 16 and 17, which tracks are indicated in the drawings as read head 1 and read head 2. Read head 1 includes a terminal 2 inductively coupled to ground at 4. The analog section of the circuit begins by taking the inputs of the read head tracks to a first differential amplifier U1 generally shown in the drawings at 6. A parallel pair of rectifiers CR1 and CR2 are clamped in parallel across the inputs of the differential amplifier 6. The output from the differential amplifier is supplied to tie point 1, indicated at TP1 in the drawings, which output is indicative of the flux reversal at either track of a magnetic read head schematically indicated at 16 and 17.

#In the description of the figures the circuit components are illustrated with their corresponding impedance values. The designations U1 through U14 in the drawings refer to integrated circuits which are identified in the chart of FIG. 2.

#Accordingly the analog section of the read electronics begins by amplifying the read head output. The amplified signal is then fed through a resistor R5 serving as the gain control to an amplifier section comprising symmetrical complimentary amplifiers 8 and 10 which cause positive going signals to appear at tie points 2 (TP2) regardless of the polarity of the flux reversal occurring at the read head. The outputs of the complimentary symmetrical amplifiers are supplied through a rectifier bridge 12 comprised of rectifiers CR3, CR4, CR5 and CR6 providing a DC threshold at TP2 to eliminate low level noise. Thus as shown in FIG. 4 the clock provides a series of 5 volt pulses occurring at a frequency determining the bit cell time Tau. The read head output provides flux reversals to be decoded, providing a zero if no flux reversal occurs during the bit cell time or providing a 1 if a flux reversal of 10 millivolts appears at Tau/2. The output of the differential amplifier 6 provides an amplified 500 millivolt signal at TP1. At TP2 the complimentary symmetrical amplifiers provide a 4 volt peak positive outgoing signal with a 1.0 volt DC threshold level impressed to eliminate noise. Between tie point 2 and tie point 3 (TP3), to achieve the most accurate input information, this series of 4 volt signals is supplied to a clipper 14 and to a differential amplifier 16 serving as a peak detector so that an output pulse occurs at TP3 at the maximum amplitude of the input signal. The output of the differential amplifier 16 is supplied through a Schmidt trigger 18 and then is made compatible for TTL logic by transistor Q1. Between TP3 and tie point 4 (TP4) is a pulse width discriminator 20 used to reduce sensitivity to noise.