Fail safe digital code rate generator

Abstract

A digital code rate generator comprises a digital number generator driven by a clock running at an appropriate frequency. Preferably the digital number generator is arranged to simultaneously generate digital representations for a plurality of different numbers. These different digital representations are provided to a selector which passes one of said digital representations to an accumulator. The accumulator continually sums the digital representations provided to it by the selector. An output of the accumulator is connected to an overflow detector which is distinctively operated when the sum of the digital representations provided to the accumulator exceeds the capacity of the accumulator. By selecting the frequency of the clock and the particular digital representation which passes the selector, the rate of operation of the overflow detector can be controlled. The output of the overflow detector thus comprises any one of a number of selectable digitally generated code rates. In another embodiment of the invention the output of the overflow detector is connected to an NAND gate whose other input is provided by the output of a divider, whose input is connected to the clock. The divider is so arranged that its output constitutes the signal carrier in a signaling system. The output of the NAND gate thus comprises a coded carrier which is turned on and off at the code rate generated by the digital code rate generator.

Dependencies are inferred from the claim text.