Self-isolating cross-coupled sense amplifier latch circuit

An improved circuit comprising:

• first and second field effect transistors each having source, drain, and gate electrodes, said source electrodes being electrically connected, said drain electrode of said first field effect transistor being electrically connected to the gate electrode of said second field effect transistor, said drain electrode of said second field effect transistor being electrically connected to the gate electrode of said first field effect transistor;
• a third field effect transistor having a source, drain and gate electrode, the drain electrode of said third field effect transistor being electrically connected to said electrical connection between said source electrodes of said first and second field effect transistors, the gate electrode of said third field effect transistor being electrically connected to a pulsating source of potential;
• a fourth field effect transistor having a source, drain and gate electrode, having its drain electrode electrically connected to a first fixed source of potential, its gate and source electrodes being electrically coupled to each other and to the connection between the drain electrode of said first field effect transistor and the gate electrode of said second field effect transistor thereby providing a first output point;
• a fifth field effect transistor having a source, drain, and gate electrode, said drain electrode being electrically connected to said first fixed source of potential, the gate and source electrodes being electrically coupled to each other and to the electrical connection between the drain electrode of said second field effect transistor and the gate electrode of said first field effect transistor thereby providing a second output point;
• a sixth field effect transistor having a drain, source and gate electrodes, having its drain and gate electrodes coupled to each other and to said first output point, its source electrode being electrically connected to a first input point;
• a seventh field effect transistor having a drain, source and gate electrode, having its drain and gate electrodes coupled to each other and to said second output point, the source electrode of said seventh field effect transistor being coupled to a second input point;
• and
• the source electrode of said third field effect transistor being coupled to a second fixed source of potential.

In an electronic memory system, a sense amplifier latching circuit comprising:

• first and second sources of potential;
• first and second input nodes;
• first and second output nodes;
• first and second transistors, each having first and second controlled electrodes and a control electrode, said first controlled electrodes being electrically connected, said second controlled electrode of said first transistor being electrically connected to the control electrode of said second transistor, said second controlled electrode of said second transistor being electrically connected to the control electrode of said first transistor;
• said first output node being in electrical contact with said electrical connection between the second controlled electrode of said first transistor and the control electrode of said second transistor;
• said second output node being in electrical contact with said electrical connection between said second controlled electrode of said second transistor and the control electrode of said first transistor;
• a first impedance means electrically connected between said first source of potential and said first output node;
• a second impedance means electrically connected between said first source of potential and said second output node;
• a first isolation means electrically connected between said first input node and said first output node;
• a second isolation means electrically connected between said second input node and said second output node;
• and
• a third transistor having first and second controlled electrodes and a control electrode, the first controlled electrode of said third transistor being electrically connected to said second source of potential, the second controlled electrode of said third transistor being in electrical contact with said electrical connection between the first controlled electrodes of said first and second transistors, the control electrode of said third transistor being electrically connected to a third source of potential.