Negative resistance device
AssigneeMatsushita Electronics Corporation
InventorsSusumu Koike, Gota Kano, Iwao Teramoto
Life of this patent
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Abstract
A negative resistance device formed by series-connection of a complementary pair of insulated gate type FETs (field effect transistors), the source of the FETs being connected to each other and the gates of each of the FETs being connected to the respective drain of the other FET at least one FET having a double layered gate insulation film under the gate electrode, thereby forming a non-volatile memory element. The negative resistance device acquires or loses negative resistance characteristics by responding to signals to the gates, thereby memorizing the signals and resulting in a highly efficient memory which requires little power in writing-in, erasing and memory-holding.
Claims19
A negative resistance device comprising:
- a complementary pair of FETs, each of which operates in depletion mode and includes a first pair of regions defining a source and drain and a second gate region and which are connected in series with each other by a first region of one FET connected to a first region of the other FET and by a gate region of each FET connected to at least one first region of the other FET, and
- a pair of external terminals respectively connected to a first region of each of said FETs which is not connected to the other FET
- at least one of said FETs being an insulated gate type non-volatile memory device comprising, at the gate region, an insulation film which stores electric charge therein to memorize in non-volatile manner.
A negative resistance memory matrix comprising a plurality of devices connected between horizontal and vertical lines, each device comprising:
- a complementary pair of FETs, each of which operates in depletion mode and includes a first pair of regions defining a source and drain and a second gate region and which are connected in series with each other by a first region of one FET connected to a first region of the other FET and by a gate region of each FET connected to at least one first region of the other FET, and
- a pair of external terminals respectively connected to a first region of each of said FETs which is not connected to the other FET,
- at least one of said FETs being an insulated gate type non-volatile memory device comprising, at the gate region, an insulation film which stores electric charge therein to memorize in non-volatile manner,
- memorizing in each device being carried out by a D.C. writing voltage of a specified polarity and amplitude exceeding a threshold value, erasing by a D.C. voltage of opposite polarity to that of said writing voltage and amplitude exceeding said threshold value and reaching by other voltages of the same polarity as said writing voltage and amplitude such that a current is obtained in the .LAMBDA. letter voltage-current characteristic of the device.
Dependencies are inferred from the claim text.