Semiconductor logic gates

A semiconductor logic gate including at least two field effect transistors having sources connected together to provide a first input terminal, gate electrodes providing two further input terminals, and respective drain electrodes, at least two input signal paths connected to said further input terminals, separate direct current paths from the first input terminal to each of the further input terminals for producing a potential input after the first input terminal dependent on the potentials at the further input terminals with no functionally effective signal path between the further input terminals, and means connecting said drain electrodes to a common output terminal for deriving an output from said logic gate in response to input signal levels present at said further input terminals.

An integrated TTL compatible semiconductor logic circuit including two logic gates each having at least one multi-emitter NPN transistor including a base terminal and first and second emitters defining respective signal input terminals, means for causing a potential difference between said emitters only in response to logic signals of different logic levels at both of said input terminals and comprising separate direct current paths from said emitters to said base terminal with no functionally effective signal paths between said emitters and said transistor having a collector connected to an output terminal for said logic gate;

• and wherein the output terminal of one of said logic gates is connected to one of the input terminals of the other logic gate.

An integrated TTL compatible semiconductor logic circuit including a plurality of logic gates each having at least one multi-emitter NPN transistor including a base terminal and first and second emitters defining respective signal input terminals, means for causing a potential difference between said emitters only in response to logic signals of different logic levels at both of said input terminals and comprising separate direct current paths from said emitters to said base terminal with no functionally effective signal paths between said emitters and said transistor having a collector connected to an output terminal for said logic gate;

• and means connecting the output terminal of each said logic gate to a common circuit output.

An integrated TTL compatible semiconductor logic gate including at least one multi-emitter NPN transistor including a base terminal and first and second emitters having terminals defining respective signal input terminals, means for causing a potential difference between said emitters only in response to logic signals of different logic levels at both of said input terminals and comprising first and second diodes having anodes connecting said first and second emitters respectively and having cathodes connected by a common resistor to said base terminal, a third input terminal connected by a third diode having a cathode connected to the cathodes of said first and second diodes, and said transistor having a collector connected to an output terminal for said logic gate.

A logic circuit having a semiconductor logic state including at least two field effect transistors having sources connected together to provide a first input terminal, gate electrodes providing two further input terminals, and respective drain electrodes, at least two input signal paths connected to said further input terminals, separate direct current paths from the first input terminal to each of the further input terminals for producing a potential input after the first input terminal dependent on the potentials at the further input terminals with no functionally effective signal path between the further input terminals, and means connecting said drain electrodes to a common output terminal for deriving an output from said logic gate in response to input signal levels present at said further input terminals;

• and a third field effect transistor having a source connected to the sources of said first and second transistors, a gate connected to an additional input terminal and by a direct current path to the source of said transistor;
• and means connecting the drain of said third transistor to said common output terminal.