Programmable data envelope detector

Apparatus for detecting the presence of a data envelope containing a predetermined number of preamble pulses, a plurality of data pulses, and a predetermined number of postamble pulses, for use with a source of pulses, a source of first timing signals, and a source of second timing signals, said pulses and said first timing signals being in substantial synchronization with one another, said first timing signals having twice the frequency of said second timing signals, said apparatus including:

• a three-count serial up-down counter responsive to said source of pulses and to said sources of first and second timing signals, said three-count generating a first signal when three of said preamble pulses have been counted and generating a second signal when five of said first timing signals have been counted after the last pulse in said postamble has been counted;
• first and second multicount up-down counters each having a count-up input lead and a count-down lead, said first multicount counter further comprising a carry output lead connected to the count-up input lead of said second multicount counter, a borrow output lead connected to the count-down input lead of said second multicount counter, and a further output lead representing a binary count-of-8, said second multicount counter further comprising a first output lead representing a binary count-of-1, a second output lead representing a binary count-of-2, a third output lead representing a binary count-of-4, and a fourth output lead representing a binary count-of-8;
• a programmable store for storing a plurality of program instructions, at least one of said instructions representing a predetermined number of preamble pulses in said data envelope;
• means for decoding said at least one instruction and for generating a strobe signal and a four-bit decoded signal representing said predetermined number of preamble pulses;
• a parallel-in, parallel-out one-bit read/write memory responsive to said decoding means for storing said decoded four-bit signal when activated by said strobe signal and for continuously generating said four-bit decoded signal over four output leads;
• at least one potential source;
• a binary comparison circuit comprising first and second five-bit groups of input leads and an output lead, the lowest order lead of each of said groups being connected to said at least one potential source, the remaining four input leads of said first group being connected to said four output leads of said read/write memory, the second lowest order lead of said second group being connected to said count-of-8 output lead of said first multicount counter, the third lowest order lead of said group being connected to said count-of-1 output lead of said second multicount counter, the fourth lowest order lead of said second group being connected to said count-of-2 output lead of said second multicount counter, and the highest order lead of said second group being connected to said count-of-4 output lead of said second multicount counter;
• a latching circuit comprising a J/K flip-flop having J, K, and C input leads, and Q and Q output leads, said J input lead being connected to the output lead of said comparison circuit, said K input lead being connected to said fourth output lead of said second multicount counter, said C input lead being responsive to said source of first timing signals;
• first logic means responsive to said first signal from said three-count counter, to said source of pulses, and to said Q output lead of said J/K flip-flop, said first logic means having an output connected to said count-up lead of said first multicount counter;
• and
• second logic means responsive to said second output signal from said three-count counter, to said source of first timing signals, and to said fourth output lead of said second multicount counter, said second logic means having an output lead connected to the count-down input lead of said first multicount counter.