Stuffing channel unit for telephone PCM system
AssigneeTRW Inc.
InventorPaul E. Drapkin
Life of this patent
Estimating the term…
Abstract
A stuff system for converting a 50 KBS pulse train to standard 64 KBS provides a 3 bit 101 and 5 bit 01001 control bit stuffing code which tolerates both single and double errors without producing an out-of-frame condition.
Claims10
A time division transmission system for an asynchronous pulse train having means for converting the pulse repetition rate (PRR) of said pulse train to a higher PRR, by the insertion of stuff pulses, so that the resultant pulse train has a PRR which is synchronous with a predetermined and fixed frequency of a common, time-divided transmission facility, said resultant pulse train having a channel word with data bits and a control bit a predetermined plurality of said channel words constituting a frame, said system comprising means for inserting stuff pulses in said pulse train in one of said channel words in accordance with a sequential control bit code having sequences of long and short lengths where said long length provides a lower stuffing rate corresponding to a PRR less than said PRR of said asynchronous pulse train and said short length provides higher stuffing rate corresponding to a PRR greater than such pulse train, said system including receiving means responsive to said control bit code for removing said stuff pulses from said resultant pulse train.
A time division transmission system for an asynchronous pulse train having means for converting the pulse repetition rate (PRR) to a higher PRR by the insertion of stuff pulses in a channel word of said time division system to a predetermined plurality of said channel words constituting a frame of said system comprising transmission means for inserting stuff pulses in said pulse train in one of said channel words and for inserting control bits in the same word, and means for receiving said pulse train and decoding a sequence of said control bits for framing said one channel and for detecting and removing said stuff pulses said decoding means sensing control bit sequences of two different lengths the long length corresponding to a low stuffing rate and the shorter length a higher stuffing rate.
A time division transmission system for an asynchronous pulse train having means for converting the pulse repetition rate (PRR) to a higher PRR by the insertion of stuff pulses in a channel word of said time division system to a predetermined plurality of said channel words constituting a frame of said system comprising transmission means for inserting stuff pulses in said pulse train in one of said channel words and for inserting control bits in the same word, and means for receiving said pulse train and decoding a sequence of said control bits for framing said one channel and for detecting and removing said stuff pulses said receiving means including a phase locked loop having variable frequency selection means connected to a fixed frequency of said system, a variable counter driven by a decoded sequence of said control bits said decode sequence indicating the total number of data bits per frame, and frequency control means coupled from said variable counter to said frequency selection means.
A time division transmission system for an asynchronous pulse train having means for converting the pulse repetition rate (PRR) of said pulse train to a higher PRR by the insertion of stuff pulses in a channel word of said time division system, a predetermined plurality of said channel words constituting a frame, said system having a channel counter clock frequency said system comprising:
- transmission means for inserting stuff pulses in said pulse train in one of said channel words and for providing on said pulse train destuffing instructions;
- means for receiving said pulse train and sensing said destuffing instructions including elastic storage means having parallel inputs for accepting a variable number of data bits of a channel word in accordance with said destuffing instructions and a serial output for providing said PRR of said asynchronous pulse train said storage means also including a parallel load-in control input for initiating parallel transfer of bits into said storage means and a serial shift-out control input, said receiving means also including phase locked loop means locked to said channel counter clock frequency and connected to a fixed frequency of said system to provide said PRR of said asynchronous pulse train to serve as said serial shift-out control signal, said loop also including a variable divider driven by said sensed destuffing instructions and having an output serving as said parallel load-in control input.
Dependencies are inferred from the claim text.