Digital electronic ignition spark timing system

A digital electronic ignition spark timing system applicable to an associated internal combustion engine for producing ignition initiating signals for effecting the interruption of the engine ignition system ignition coil primary winding energizing circuit, comprising:

• means for producing a series of electrical signal pulses of a substantially constant preselected frequency;
• means for producing a timing signal for each cylinder of said engine at a selected engine crankshaft position in degrees relative to piston top dead center;
• a counter circuit for counting said electrical signal pulses during each engine timing count period between successive said timing signals and producing a running total output binary coded number of said electrical signal pulses counted;
• circuit means for accepting upon the initiation of each said engine timing count period the said counter circuit running total output binary coded total number of said electrical signal pulses counted during the previous said engine timing count period and for storing this binary coded number until the initiation of the next said engine timing count period;
• means responsive to said stored binary coded number for producing an output first binary code representation of the fractional portion of said stored binary coded number that the predetermined number of crankshaft degrees ignition spark engine speed advance corresponding to the engine speed at which said stored binary coded number of said electrical signal pulses may be counted during one said engine timing count period is of the number of engine crankshaft degrees between successive said timing signals;
• means responsive to the intake manifold vacuum of said engine for producing digital signal representations thereof;
• means responsive to said digital signal representations of intake manifold vacuum for producing output ignition spark vacuum advance binary code representations of the predetermined number of crankshaft degrees ignition spark vacuum advance corresponding to the said intake manifold vacuum;
• means responsive to one of said ignition spark vacuum advance binary code representations and said stored binary coded number for producing a second binary code representation of the quotient of the product of said ignition spark vacuum advance binary code representation multiplied by said stored binary coded number divided by the number of engine crankshaft degrees between successive said timing signals;
• means for producing a third binary code representation of the sum of said first and second binary code representations;
• means for producing a fourth binary code representation of the difference between said stored binary coded number and said third binary code representation;
• a comparator circuit responsive to said fourth binary code representation and said counter circuit running total output binary coded numbers for producing an ignition initiating signal when one of said running total output binary coded numbers of said counter circuit is equal to said fourth binary code representation;
• and
• circuit means responsive to each of said ignition initiating signals for interrupting said engine ignition system ignition coil primary winding energizing circuit.

A digital electronic ignition spark timing system applicable to an associated internal combustion engine for producing ignition initiating signals for effecting the interruption of the engine ignition system ignition coil primary winding energizing circuit, comprising:

• an oscillator circuit for producing a series of electrical signal pulses of a substantially constant preselected frequency;
• means for producing a timing signal for each cylinder of said engine at a selected engine crankshaft position in degrees relative to piston top dead center;
• a counter circuit for counting said electrical signal pulses during each engine timing count period between successive said timing signals and producing a running total output binary coded number of said electrical signal pulses counted;
• a first register circuit for accepting upon the initiation of each said engine timing count period the said counter circuit running total output binary coded total number of said electrical signal pulses counted during the previous said engine timing count period and for storing this binary coded number until the initiation of the next said engine timing count period;
• a first read only memory means preprogrammed to produce, in response to said stored binary coded number, an output first binary code representation of the fractional portion of said stored binary coded number that the predetermined number of crankshaft degrees ignition spark engine speed advance corresponding to the engine speed at which said stored binary coded number of said electrical signal pulses may be counted during one said engine timing count period is of the number of engine crankshaft degrees between successive said timing signals;
• means including an engine vacuum sensor and an analog to digital converter circuit responsive to the intake manifold vacuum of said engine for producing digital signal representations thereof;
• a second read only memory means preprogrammed to produce, in response to said digital signal representations of intake manifold vacuum, an output ignition spark vacuum advance binary code representation of the predetermined number of crankshaft degrees ignition spark vacuum advance corresponding to the said intake manifold vacuum;
• a second register circuit for accepting upon the initiation of each said engine timing count period the said second read only memory means output ignition spark vacuum advance binary code representation and for storing this ignition spark vacuum advance binary code representation until the initiation of the next said engine timing count period;
• a digital arithmetic logic unit responsive to said ignition spark vacuum advance binary code representation stored in said second register circuit and said binary coded number stored in said first register circuit means for producing a second binary code representation of the quotient of the product of said ignition spark vacuum advance binary code representation multiplied by said stored binary coded number divided by the number of engine crankshaft degrees between successive said timing signals;
• a binary adder circuit for producing a third binary code representation of the sum of said first and second binary code representations;
• a binary subtractor circuit for producing a fourth binary code representation of the difference between said binary coded number stored in said first register circuit means and said third binary code representation;
• a comparator circuit responsive to said fourth binary code representation and said counter circuit running total output binary coded numbers for producing an ignition initiating signal when one of said running total output binary coded numbers of said counter circuit is equal to said fourth binary code representation;
• and
• circuit means responsive to each of said ignition initiating signals for interrupting said engine ignition system ignition coil primary winding energizing circuit.

A digital electronic ignition spark timing system applicable to an associated internal combustion engine for producing dwell and ignition initiating signals for effecting, respectively, the completion and interruption of the engine ignition system ignition coil primary winding energizing circuit, comprising:

• means for producing a series of electrical signal pulses of a substantially constant preselected frequency;
• means for producing a timing signal for each cylinder of said engine at a selected engine crankshaft position in degrees relative to piston top dead center;
• a first counter circuit for counting said electrical signal pulses during each engine timing count period between successive said timing signals and producing a running total output binary coded number of said electrical signal pulses counted;
• circuit means for accepting upon the initiation of each said engine timing count period the said first counter circuit running total output binary coded total number of said electrical signal pulses counted during the previous said engine timing count period and for storing this binary coded number until the initiation of the next said engine timing count period;
• means responsive to said stored binary coded number for producing an output first binary code representation of the fractional portion of said stored binary coded number that the predetermined number of crankshaft degrees ignition spark engine speed advance corresponding to the engine speed at which said stored binary coded number of said electrical signal pulses may be counted during one said engine timing count period is of the number of engine crankshaft degrees between successive said timing signals;
• means responsive to the intake manifold vacuum of said engine for producing digital signal representations thereof;
• means responsive to said digital signal representations of intake manifold vacuum for producing output ignition spark vacuum advance binary code representations of the predetermined number of crankshaft degrees ignition spark vacuum advance corresponding to the said intake manifold vacuum;
• means responsive to one of said ignition spark vacuum advance binary code representations and said stored output binary coded number of said first counter circuit for producing a second binary code representation of the quotient of the product of said ignition spark vacuum advance binary code representation multiplied by said stored binary coded number divided by the number of engine crankshaft degrees between successive said timing signals;
• means for producing a third binary code representation of the sum of said first and second binary code representations;
• means for producing a fourth binary code representation of the difference between said stored output binary coded number of said first counter circuit and said third binary code representation;
• a first comparator circuit responsive to said fourth binary code representation and said first counter circuit running total output binary coded numbers for producing an ignition initiating signal when one of said running total output binary coded numbers of said first counter circuit is equal to said fourth binary code representation;
• a second counter circuit for counting said electrical signal pulses during each ignition dwell count period between successive said ignition initiating signals and producing a running total output binary coded number of said electrical signal pulses counted;
• circuit means for accepting upon the initiation of each said ignition dwell count period the said second counter circuit running total output binary coded total number of said electrical signal pulses counted during the previous said ignition dwell count period and for storing this binary coded number until the initiation of the next said ignition dwell count period;
• means responsive to said stored output binary coded number of said second counter circuit for producing a fifth binary code representation of the difference between this said stored binary coded number and a predetermined constant number;
• a second comparator circuit responsive to said fifth binary code representation and said second counter circuit running total output binary coded numbers for producing an output signal when one of said second counter circuit running total output binary coded numbers is equal to said fifth binary code representation;
• means responsive to said output signal of said second comparator circuit for producing a first dwell initiating signal enabling signal;
• means for producing a logic signal in response to a predetermined said second counter circuit running total output binary coded number;
• means responsive to said logic signal for producing a second dwell initiating signal enabling signal;
• means responsive to said first and second enabling signals for producing a dwell initiating signal;
• and
• circuit means responsive to each of said dwell initiating signals and each of said ignition initiating signals for completing and interrupting, respectively, said engine ignition system ignition coil primary winding energizing circuit.

A digital electronic ignition spark timing system applicable to an associated internal combustion engine for producing dwell and ignition initiating signals for effecting, respectively, the completion and interruption of the engine ignition system ignition coil primary winding energizing circuit, comprising:

• means for producing a series of electrical signal pulses of a substantially constant preselected frequency;
• means for producing a timing signal for each cylinder of said engine at a selected engine crankshaft position in degrees relative to piston top dead center;
• a first counter circuit for counting said electrical signal pulses during each engine timing count period between successive said timing signals and producing a running total output binary coded number of said electrical signal pulses counted;
• a first register circuit for accepting upon the initiation of each said engine timing count period the said first counter circuit running total output binary coded total number of said electrical pulses counted during the previous said engine timing count period and for storing this binary coded number until the initiation of the next said engine timing count period;
• a first read only memory means preprogrammed to produce, in response to said stored binary coded number, an output first binary code representation of the fractional portion of said stored binary coded number that the predetermined number of crankshaft degrees ignition spark engine speed advance corresponding to the engine speed at which said stored binary coded number of said electrical signal pulses may be counted during one said engine timing count period is of the number of engine crankshaft degrees between successive said timing signals;
• means including a vacuum sensor and an analog to digital converter circuit responsive to the intake manifold vacuum of said engine for producing digital signal representations thereof;
• a second read only memory means preprogrammed to produce, in response to said digital signal representations of intake manifold vacuum, an output ignition spark vacuum advance binary code representation of the predetermined number of crankshaft degrees ignition spark vacuum advance corresponding to the said intake manifold vacuum;
• a second register circuit for accepting upon the initiation of each said engine timing count period the said second read only memory means output ignition spark vacuum advance binary code representation and for storing this ignition spark vacuum advance binary code representation until the initiation of the next said engine timing count period;
• a digital arithmetic logic unit responsive to said ignition spark vacuum advance binary code representation stored in said second register circuit and said binary coded number stored in said first register circuit for producing a second binary code representation of the quotient of the product of said ignition spark vacuum advance binary code representation multiplied by said stored binary coded number divided by the number of engine crankshaft degrees between successive said timing signals;
• a binary adder circuit for producing a third binary code representation of the sum of said first and second binary code representations;
• a first binary subtractor circuit for producing a fourth binary code representation of the difference between said binary coded number stored in said first register circuit means and said third binary code representation;
• a first comparator circuit responsive to said fourth binary code representation and said first counter circuit running total output binary coded numbers for producing an ignition initiating signal when one of said running total output binary coded numbers of said first counter circuit is equal to said fourth binary code representation;
• a second counter circuit for counting said electrical signal pulses during each ignition dwell count period between successive said ignition initiating signals and producing a running total output binary coded number of said electrical signal pulses counted;
• a third register circuit for accepting upon the initiation of each said ignition dwell count period the said second counter circuit running total output binary coded total number of said electrical signal pulses counted during the previous said ignition dwell count period and for storing this binary coded number until the initiation of the next said ignition dwell count period;
• a second binary subtractor circuit responsive to said binary coded number stored in said third register circuit for producing a fifth binary code representation of the difference between this said stored binary coded number and a predetermined constant number;
• a second comparator circuit responsive to said fifth binary code representation and said second counter circuit running total output binary coded numbers for producing an output signal when one of said second counter circuit running total output binary coded numbers is equal to said fifth binary code representation;
• a first bi-stable flip-flop circuit responsive to said output signal of said second comparator circuit for producing a first dwell initiating signal enabling signal;
• a first AND gate for producing a logic signal in response to a predetermined said second counter circuit running total output binary coded number;
• a second bi-stable flip-flop circuit responsive to said logic signal for producing a second dwell initiating signal enabling signal;
• a second AND gate responsive to said first and second enabling signals for producing a dwell initiating signal;
• and
• circuit means responsive to each of said dwell initiating signals and each of said ignition initiating signals for completing and interrupting, respectively, said engine ignition system ignition coil primary winding energizing circuit.

A digital electronic ignition spark timing system applicable to an associated internal combustion engine for producing dwell and ignition initiating signals for effecting, respectively, the completion and interruption of the engine ignition system ignition coil primary winding energizing circuit, comprising:

• means for producing a series of electrical signal pulses of a substantially constant preselected frequency;
• means for producing timing signal pulses of a predetermined duration for each cylinder of said engine at a selected engine crankshaft position in degrees relative to piston top dead center;
• a first counter circuit for counting said electrical signal pulses during each engine timing count period between the leading edges of successive said timing signals and producing a running total output binary coded number of said electrical signal pulses counted;
• circuit means for accepting upon the initiation of each said engine timing count period the said first counter circuit running total output binary coded total number of said electrical signal pulses counted during the previous said engine timing count period and for storing this binary coded number until the initiation of the next said engine timing count period;
• means responsive to said stored binary coded number for producing an output first binary code representation of the fractional portion of said stored binary coded number that the predetermined number of crankshaft degrees ignition spark engine speed advance corresponding to the engine speed at which said stored binary coded number of said electrical signal pulses may be counted during one said engine timing count period is of the number of engine crankshaft degrees between successive said timing signals;
• means responsive to the intake manifold vacuum of said engine for producing digital signal representations thereof;
• means responsive to said digital signal representations of intake manifold vacuum for producing output ignition spark vacuum advance binary code representations of the predetermined number of crankshaft degrees ignition spark vacuum advance corresponding to the said intake manifold vacuum;
• means responsive to one of said ignition spark vacuum advance binary code representations and said stored output binary coded number of said first counter circuit for producing a second binary code representation of the quotient of the product of said ignition spark vacuum advance binary code representation multiplied by said stored binary coded number divided by the number of engine crankshaft degrees between successive said timing signals;
• means for producing a third binary code representation of the sum of said first and second binary code representations;
• means for producing a fourth binary code representation of the difference between said stored output binary coded number of said first counter circuit and said third binary code representation;
• a first comparator circuit responsive to said fourth binary code representation and said first counter circuit running total output binary coded numbers for producing an ignition initiating signal when one of said running total output binary coded numbers of said first counter circuit is equal to said fourth binary code representation;
• a second counter circuit for counting said electrical signal pulses during each ignition dwell count period between successive said ignition initiating signals and producing a running total output binary coded number of said electrical signal pulses counted;
• circuit means for accepting upon the initiation of each said ignition dwell count period the said second counter circuit running total output binary coded total number of said electrical signal pulses counted during the previous said ignition dwell count period and for storing this binary coded number until the initiation of the next said ignition dwell count period;
• means responsive to said stored output binary coded number of said second counter circuit for producing a fifth binary code representation of the difference between this said stored binary coded number and a predetermined constant number;
• a second comparator circuit responsive to said fifth binary code representation and said second counter circuit running total output binary coded numbers for producing an output signal when one of said second counter circuit running total output binary coded numbers is equal to said fifth binary code representation;
• means responsive to said output signal of said second comparator circuit for producing a first dwell initiating signal enabling signal;
• means for producing a logic signal in response to a predetermined said second counter circuit running total output binary coded number;
• means responsive to said logic signal for producing a second dwell initiating signal enabling signal;
• means responsive to said first and second enabling signals for producing a dwell initiating signal;
• circuit means responsive to each of said dwell initiating signals and each of said ignition initiating signals for completing and interrupting, respectively, said engine ignition system ignition coil primary winding energizing circuit;
• means for producing an engine crank mode logic signal while said engine is being cranked;
• and
• circuit means responsive to said timing signal pulses and said engine crank mode logic signals for effecting the interruption and completion of said engine ignition system ignition coil primary winding energizing circuit in response to the leading and trailing edges, respectively, of each of said timing signal pulses while said engine is being cranked.

A digital electronic ignition spark timing system applicable to an associated internal combustion engine for producing dwell and ignition initiating signals for effecting, respectively, the completion and interruption of the engine ignition system ignition coil primary winding energizing circuit, comprising:

• means for producing a series of electrical signal pulses of a substantially constant preselected frequency;
• means for producing a timing signal pulse of a predetermined duration for each cylinder of said engine at a selected engine crankshaft position in degrees relative to piston top dead center;
• a first counter circuit for counting said electrical signal pulses during each engine timing count period between the leading edges of successive said timing signals and producing a running total output binary coded number of said electrical signal pulses counted;
• a first register circuit for accepting upon the initiation of each said engine timing count period the said first counter circuit output running total output binary coded total number of said electrical signal pulses counted during the previous said engine timing count period and for storing this binary coded number until the initiation of the next said engine timing count period;
• a first read only memory means preprogrammed to produce, in response to said stored binary coded number, an output first binary code representation of the fractional portion of said stored binary coded number that the predetermined number of crankshaft degrees ignition spark engine speed advance corresponding to the engine speed at which said stored binary coded number of said electrical signal pulses may be counted during one said engine timing count period is of the number of engine crankshaft degrees between successive said timing signals;
• means including a vacuum sensor and an analog to digital converter circuit responsive to the intake manifold vacuum of said engine for producing digital signal representations thereof;
• a second read only memory means preprogrammed to produce, in response to said digital signal representations of intake manifold vacuum, an output ignition spark vacuum advance binary code representation of the predetermined number of crankshaft degrees ignition spark vacuum advance corresponding to the said intake manifold vacuum;
• a second register circuit for accepting upon the initiation of each said engine timing count period the said second read only memory means output ignition spark vacuum advance binary code representation and for storing this ignition spark vacuum advance binary code representation until the initiation of the next said engine timing count period;
• a digital arithmetic logic unit responsive to said ignition spark vacuum advance binary code representation stored in said second register circuit and said binary coded number stored in said first register circuit for producing a second binary code representation of the quotient of the product of said ignition spark vacuum advance binary code representation multiplied by said stored binary coded number divided by the number of engine crankshaft degrees between successive said timing signals;
• a binary adder circuit for producing a third binary code representation of the sum of said first and second binary code representations;
• a first binary subtractor circuit for producing a fourth binary code representation of the difference between said binary coded number stored in said first register circuit and said third binary code representation;
• a first comparator circuit responsive to said fourth binary code representation and said first counter circuit running total output binary coded numbers for producing an ignition initiating signal when one of said running total output binary coded numbers of said first counter circuit is equal to said fourth binary code representation;
• a second counter circuit for counting said electrical signal pulses during each ignition dwell count period between successive said ignition initiating signals and producing a running total output binary coded number of said electrical signal pulses counted;
• a third register circuit for accepting upon the initiation of each said ignition dwell count period the said second counter circuit running total output binary coded total number of said electrical signal pulses counted during the previous said ignition dwell count period and for storing this binary coded number until the initiation of the next said ignition dwell count period;
• a second binary subtractor circuit responsive to said binary coded number stored in said third register circuit for producing a fifth binary code representation of the difference between this said stored binary coded number and a predetermined constant number;
• a second comparator circuit responsive to said fifth binary code representation and said second counter circuit running total output binary coded numbers for producing an output signal when one of said second counter circuit running total output binary coded numbers is equal to said fifth binary code representation;
• a first bi-stable flip-flop circuit responsive to said output signal of said second comparator circuit for producing a first dwell initiating signal enabling signal;
• a first AND gate for producing a logic signal in response to a predetermined said second counter circuit running total output binary coded number;
• a second bi-stable flip-flop circuit responsive to said logic signal for producing a second dwell initiating signal enabling signal;
• a second AND gate responsive to said first and second enabling signals for producing a dwell initiating signal;
• circuit means responsive to each of said dwell initiating signals and each of said ignition initiating signals for completing and interrupting, respectively, said engine ignition system ignition coil primary winding energizing circuit;
• means for producing an engine crank mode logic signal while said engine is being cranked;
• and
• circuit means responsive to said timing signal pulses and said engine crank mode logic signals for effecting the interruption and completion of said engine ignition system ignition coil primary winding energizing circuit in response to the leading and trailing edges, respectively, of each of said timing signal pulses while said engine is being cranked.