Low cost remote control receiver

In a television broadcast receiver, a remote control receiver for receiving continuous wave command signal pulses of different operating frequencies in individual signal channels within a selected frequency range, said receiver having an individual output for each said signal channel, means for dividing the frequency of received command signal pulses by a predetermined factor to produce sequence control pulses;

• sequence generator means responsive to each sequence control pulse resulting from reception of a command signal within the selected frequency range to initiate a new counting cycle;
• reference frequency counter means for counting reference frequency pulses in each of said counting cycles;
• said command signal pulses in each channel giving rise to a different count of said reference frequency counter means during a counting cycle;
• sequence generator means responsive to each said predetermined count of command signal pulses within said selected frequency range to initiate a fresh counting cycle;
• storage means for storing the count of the reference frequency counter reached during a counting cycle;
• comparator circuit means for comparing at the end of each said counting cycle the count of said reference frequency counter means with the existing count stored by said storage means and for producing a first signal indicating identity between such counts and a second signal indicating non-identity between said counts;
• decoder circuit means connected for receiving the count of said storage means to generate an output signal at an output of said receiver determined by said count;
• validation means selectively actuable to transfer the count of said storage means to said decoder circuit means;
• control circuit means connected for receiving said first signals and said second signals and for applying an actuating signal to said validating means only after receipt of a predetermined number of said first signals and to apply a de-actuating signal to said validation means only after receipt of a predetermined number of consecutive second signals;
• up/down counter means having n stages, where n is an integer, means connecting first and second outputs of said decoder circuit means to respective input gating means for controlling application of clock pulses to up and down inputs of said up/down counter;
• digital word to duty cycle converter means for receiving input pulses at a selected frequency, said converter means having n rate inputs, means connecting said n stages of said up/down counter means to respective ones of said n rate inputs to apply a digit word thereto to control the output duty cycle of said converter means as a function of the count of said up/down counter means;
• said broadcast receiver further including manually operable switch means connected in parallel with individual ones of said remote control receiver outputs for operation to produce an output signal thereat.

Remote control receiver for receiving continuous wave command signal pulses of different operating frequencies in individual signal channels within a selected frequency range, said receiver having an individual output for each said signal channel, means for dividing the frequency of received command signal pulses by a predetermined factor to produce sequence control pulses;

• sequence generator means responsive to each sequence control pulse resulting from reception of a command signal within the selected frequency range to initiate a new counting cycle;
• reference frequency counter means for counting reference frequency pulses having a frequency significantly higher than that of said command signal pulses in each of said counting cycles said reference frequency counter means comprising m stages and having a counting capacity of 2.sup.m ;
• storage means connected to selected ones of the stages of said reference counter means and operable to receive and store a digital word from the reference frequency counter means stage to which it is connected;
• said command signal pulses in each channel giving rise to a different digital word in said selected stages of said reference frequency counter means during a counting cycle;
• comparator circuit means for comparing at the end of each said counting cycle the digital word in said selected stages of the reference frequency counter means with the digital word stored by said storage means and for producing a first signal indicating identity between said digital words and a second signal indicating non-identity between said digital words;
• decoder circuit means connected to said storage means to generate an output signal at an output of said receiver determined by the digital word stored therein;
• validation means selectively actuable to transfer the contents of said storage means to said decoder circuit means;
• control circuit means connected for receiving said first signals and said second signals and for applying an actuating signal to said validating means only after receipt of a predetermined number of said first signals and to apply a deactuating signal to said validation means only after receipt of a predetermined number of consecutive second signals.