Process for preparing a substrate for MOS devices of different thresholds
AssigneeIntel Corporation
InventorRichard D. Pashley
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Abstract
In a substrate, a process for forming a plurality of host regions of different conductivity types and dopant concentration levels. These various host regions include the channels of MOS field-effect devices, thereby providing devices of different voltage thresholds. Overlapping masking and doping provides numerous host regions with a minimum of masking.
Claims13
In the fabrication of MOS devices, a process for preparing a silicon substrate comprising the steps of:
- a. forming a first masking means over a first area of said substrate;
- b. subjecting said substrate to a first dopant such that portions thereof other than said first area of said substrate are doped with said first dopant;
- c. forming a second masking means over a second area of said substrate, said second area being coextensive with a portion of said first area;
- d. subjecting said substrate to a second dopant such that portions thereof other than said second area of said substrate are doped with said second dopant;
- said steps (a) through (d) resulting in four host regions in said substrate each having a different doping level such that when a field-effect transistor is formed in each of said host regions each such transistor may have a different threshold voltage;
- fabricating MOS devices in said host regions, each having a different threshold voltage.
A process for preparing a p-type silicon substrate such that a plurality of devices of different threshold voltages may be fabricated on said substrate comprising the steps of:
- a. forming an oxide on said substrate;
- b. removing a portion of said oxide from said substrate so as to expose a first and second area on said substrate;
- c. subjecting said substrate to an n-type dopant such that said first and second areas of said substrate are doped;
- d. forming a masking layer on said substrate, said masking layer covering said second area and a fourth area and said masking layer leaving exposed said first area and a third area;
- e. subjecting said substrate to a p-type dopant so as to simultaneously dope said first and third areas;
- said steps (a) through (e) resulting in four host regions in said substrate each having a different doping level such that when a field-effect transistor is formed in each of said host regions each such transistor may have a different threshold voltage;
- fabricating MOS devices in said host regions, each having a different threshold voltage.
Dependencies are inferred from the claim text.