Multidimensional parallel access computer memory system
AssigneeBurroughs Corporation
InventorsDuncan H. Lawrie, Chandrakant Ratilal Vora
Life of this patent
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Abstract
A multidimensional parallel access computer memory system is provided to facilitate high speed parallel access of data from a multi-bank computer memory. The system is particularly adapted to matrix calculations whereby matrix elements along linear matrix vectors are nonconflictingly stored in a plurality of independent memories and are associated in parallel with a plurality of independent processors for high speed matrix manipulations. An alignment network interposing the plurality of memories and the plurality of processors responds to the generation of memory and address tags to associate a particular matrix element stored in a particular memory address with a particular processor for processing.
Claims6
A parallel data processing storage and accessing system comprising:
- a plurality of memory modules for storing a matrix and for providing non-conflicting access to matrix elements along all individual linear vectors thereof, each module in said plurality of memory modules having a plurality of addressable storing locations, each location therein capable of storing a single matrix element, the number of memory modules in said plurality thereof being relatively prime to the memory ordering of each linear vector of said matrix stored, wherein the memory ordering of each linear vector is equal to the distance between two consecutive elements therein times the increment to be accessed;
- a plurality of data processing units, each unit therein for performing data processing operations on matrix elements;
- alignment means interposing said plurality of memory modules and said plurality of data processing units for providing data communications paths between designated individual data processing units from said plurality thereof and designated individual memory modules from said plurality thereof;
- tag generating means cooperating with said alignment means and said plurality of memory modules for designating individual data processing units from said plurality thereof and individual memory modules from said plurality thereof for data communications therebetween and for addressing each memory module in said plurality thereof whereby matrix elements along all individual linear vectors of said matrix stored are non-conflictingly accessible.
Dependencies are inferred from the claim text.