US 4,051,471 A · Key input means providing common key identifying and display driving digit timing signals

Abstract

A keying input apparatus is provided which includes; a bit pattern generator responsive to a clock signal for generating different bit patterns of four bits, in a bit sequence and a decoding matrix for converting the different bit patterns at every fourth bit, into individual digit timing signals. A plurality of key switches are connected at one end thereof with corresponding ones of the digit timing signals and connected to a common terminal at the other ends thereof, to drive a gate responsive to the common connected output of said key switches for allowing a coded signal representative of a particular depressed key to be withdrawn from the bit pattern generator and transfer it to a circulation register for storing the coded signal. Depression of a given key thus enables the gate at a corresponding digit timing to load a coded signal corresponding to that digit timing in the register, so that the coded signal as stored in the register uniquely identifies the depressed key.

Claims23

Dependent claims

A keying input apparatus comprising:

means for providing sequentially different logic state pattern signals each being of a predetermined number of bits,
a plurality of output terminals,
a common terminal,
means responsive to said different logic state pattern signals for providing a plurality of individual digit timing signals applied individually in a digit timing sequence to corresponding ones of said plurality of output terminals;
a like plurality of keying input means selectively connected on one side thereof to respective ones of said plurality of output terminals and connected at the other side thereof commonly to said common terminal for applying, upon operation of any one of said keying input means, the corresponding one of said digit timing signals in said digit timing sequence to said common terminal ;
and
means responsive to a said corresponding one of said individual digit timing signals as selected through input operation of said keying input means for withdrawing from said logic state pattern signal providing means a coded signal uniquely identifying said operated keying input means.

4 more elements

A keying input apparatus, comprising:

means for providing clock pulses;
means response to said clock pulses for generating sequentially a first plurality of different logic state pattern signals, each comprising a different pattern of logic states at a plurality of bit positions;
a plurality of output terminals;
a common terminal;
means responsive to said different pattern of logic states of said plurality of bits of said sequentially provided first plurality of different logic state pattern signals for providing a plurality of individual digit timing signals in a digit timing sequence such that each digit timing signal is individualy provided at a corresponding one of said plurality of terminals;
means for displaying information, said means having a plurality of digit display positions each connected individually to a corresponding one of said plurality of output terminals to be responsive to said digit timing signals for displaying information in said digit timing sequence;
a plurality of keying input means, each having one terminal connected individually to a corresponding one of said output terminals and the other terminal connected to said common terminal for applying, upon operation of any one of said keying means the corresponding one of said individual digit timing signals in said digit timing sequence to said common terminal;
means responsive to said clock pulses for generating a plurality of bit timing signals in synchronism with said clock pulses, each of said plurality of digit timing signal covering an interval including said plurality of bit timing signals;
means responsive to a predetermined bit timing signal of each digit timing signal and to a digit timing signal applied to said common terminal through said operated one of said keying input means for withdrawing from said logic state pattern signal providing means a corresponding logic state pattern signal at the time of said predetermined bit timing signal of said digit timing signal in the form of a coded signal uniquely identifying said operated keying input means.

6 more elements

A keying input apparatus comprising:

means for providing clock pulses defining bit timing and digit timing intervals;
means responsive to said clock pulses for generating sequentially a first predetermined plurality of different logic state pattern signals of a predetermined number of bits one at each said bit timing interval
said means for generating said first plurality of logic state pattern signals comprising
shift register means operable in response to said clock pulses comprising a plurality of logic state storing units corresponding in number to said predetermined number of bits, and
means operatively coupled to said shift register means for changing forcibly a logic state of a predetermined unit of said logic state storing units, whereby said first plurality of different logic state pattern signals each being of said predetermined number of bits are generated sequentially,
means responsive to said clock pulses and said first plurality of logic state pattern signals for generating a second plurality of logic state pattern signals one at each of said digit timing intervals,
each said digit timing interval including a plurality of bit timing intervals corresponding to said predetermined number of bits
a plurality of output terminals,
a common terminal,
means responsive to said second plurality of different logic state pattern signals for providing a plurality of individual digit timing signals in a digit timing sequence individually at said plurality of output terminals, respectively,
a plurality of keying input means connected at one end thereof individually to said plurality of output terminals and connected at the other ends thereof commonly to said common terminal for applying, upon operation of any one of said keying input means, the corresponding one of said individual digit timing signals at the corresponding digit timing interval to said common terminal,
means responsive to said clock pulses for generating a plurality of bit timing signals in synchronism with said clock pulses, each of said plurality of digit timing signals covering an interval including said plurality of bit timing signals and
means responsive to a predetermined bit timing signal of each digit timing signal and to a digit timing signal applied to said common terminal through said operated keying input means for withdrawing from said first logic state pattern signal providing means a corresponding one of said first plurality of logic state pattern signals at the time of said predetermined bit timing signal of said digit timing signal in the form of a bit series coded signal uniquely indentifying said operated keying input means.

10 more elements

Dependencies are inferred from the claim text.

Key input means providing common key identifying and display driving digit timing signals

Life of this patent

Key input means providing common key identifying and display driving digit timing signals

Life of this patent

Abstract

Claims23