Flip-flop accompanied by two current switches, one having a smaller current sink capability than the other
AssigneeNippon Electric Co., Ltd.
InventorHidemori Inukai
Life of this patent
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Abstract
A first current switching circuit is connected to a first node of a flip-flop circuit and has an input terminal. A second current switching circuit is connected to a second node of the flip-flop and has a control terminal connected to the first node and an activation terminal. The second switching circuit has a smaller current sinking capability than the first. An activation signal for activating the flip-flop is also supplied to the activation terminal. The first switching circuit may comprise decoder transistors responsive to address signals to select memory cells connected to the first node through an address line driver.
Claims8
A circuit arrangement comprising:
- a flip-flop circuit including a first field-effect transistor having a first electrode connected to a common point, a second electrode connected to a first node, and a control electrode connected to a second node, a second field-effect transistor having a first electrode connected to said common point, a second electrode connected to said second node, and a control electrode connected to said first node, and a third field-effect transistor having a first electrode connected to a reference point, a second electrode connected to said common point, and a control electrode connected to a source of an activation signal;
- precharge means connected to said first and second nodes for rendering said first node voltage higher than said second node voltage when said flip-flop circuit is in quiescent state;
- a first current switching circuit including a fourth field-effect transistor having a first electrode connected to said reference point, a second electrode connected to said first node, and a control electrode connected to an input terminal;
- and a second current switching circuit including a fifth field effect transistor having a first electrode, a second electrode connected to said second node, and a control electrode connected to said first node, and a sixth field-effect transistor having a first electrode connected to said reference point, a second electrode connected to said first electrode of said fifth transistor, and control electrode connected to the source of said activation signal;
- said second switching circuit having a smaller current sink capability than said first switching circuit.
In combination, a flip-flop circuit residing in one of a quiescent state in which direct current conduction is eliminated in said flip-flop circuit and an activated state, said flip-flop including first and second nodes, first and second field-effect transistors cross-coupled to each other at said first and second nodes;
- a first current switching circuit connected to said first node and having an input terminal for receiving an input signal;
- a second current switching circuit connected to said second node and having a control terminal connected to said first node and further having an activation terminal for receiving an activation signal, said second switching circuit having a smaller current sinking capability than said first switching circuit;
- means for switching said flip-flop circuit from said quiescent state to said activated state in response to said activation signal;
- means for precharging said first and second nodes to first and second potentials sufficient in amplitude to cause said first and second transistors to be in their conductive state, respectively, during said quiescent state, said first potential being higher than said second potential;
- whereby said first node voltage becomes opposite in its digital level to said input signal and said second node voltage becomes of substantially the same digital level as said input signal when said flip-flop circuit is switched to said activated state by said switching means.
A decoder circuit comprising an output node;
- input terminals receiving a plurality of input signals;
- a plurality of field-effect transistors connected in parallel between said output node and a reference potential, control gates of said transistors being coupled with said input terminals;
- a flip-flop circuit having a quiescent state in which direct current paths are eliminated in said flip-flop circuit and an activated state and further having a first node directly connected to said output node and a second node;
- a current switching circuit connected to said second node, said current switching circuit having a control terminal connected to said first node and an activation terminal for receiving an activation signal, said switching circuit having a smaller current sinking capability than said transistors;
- means for switching said flip-flop circuit from said quiescent state to activated state in response to said activation signal;
- means for precharging said first and second potentials, respectively, during said quiescent state of said flip-flop circuit, said first potential being higher than said second potential;
- whereby said output node directly connected to said first node becomes said reference potential when at least one of said transistors becomes the conductive state at the same time that said flip-flop circuit is switched to said activated state by said switching means.
Dependencies are inferred from the claim text.