Apparatus and method for composing digital information on a data bus
AssigneeIntel Corporation
InventorSamuel Schwartz
Life of this patent
Estimating the term…
Abstract
Logical and arithmetic shifts, rotations, and compositions of digital words can be performed directly on the data bus by use of registers which are selectively coupled to the data bus through bidirectional devices. The registers may be buffered latches having a tri-stated buffered output so that the contents of the register will not be altered by stray charges stored in the distributed capacitance of the selected data bus line.
Claims18
A digital logic circuit for the manipulation of digital signals comprising:
- an array of conductive lines forming a matrix of columns and rows;
- a plurality of bidirectional coupling means for coupling selected columns with selected rows, each of said selected columns being coupled to one of said corresponding selected rows at an intersection of said selected column with said selected row within said matrix, said bidirectional coupling means coupling said digital signals from said rows to said columns, and from said columns to said rows:
- a plurality of conductive control lines, each of said control lines being coupled to a subset of said coupling means lying along a diagonal of said matrix, said control lines communicating a control signal to each of said coupling means included in said subset on said matrix diagonal;
- and
- a plurality of register means for storing digital information, each of said register means being coupled to a different one of said columns of said matrix.
In a digital logic circuit including a matrix of conductive columns and rows coupled at selected matrix intersections of said columns and rows by bidirectional MOS devices wherein bidirectional MOS devices along each diagonal are coupled in common to a control line, a register comprising a plurality of tri-state buffered latch circuits each comprising:
- a clocked latch circuit;
- a gate selectively coupling said clocked latch circuit to said column;
- and
- a buffer circuit coupling said clocked latch circuit to one of said columns of said matrix, said buffer circuit including at least a first and second inverter stage said buffer circuit further including,
- a pull-up device to set a logical one on said column, said pull-up device coupled to said column,
- means coupling said first inverter stage to said pull-up device,
- a pull-down device to set a logical zero on said column, said pull-down device coupled to said column,
- means coupling said pull-down device to said second inverter stage, and
- disenabling means for disenabling said first and second inverter stages, said pull-up device and said pull-down device in response to a disenabling signal, said disenabling signal being coupled to said disenabling means when said clocked latch circuit is coupled through said gate to said column.
A method for simultaneously manipulating a plurality of digital signals on a plurality of ordered data bus lines in an integrated circuit comprising the steps of:
- coupling said plurality of digital signals to said plurality of ordered data bus lines, said plurality of digital signals assuming a first ordered sequence corresponding to said ordered data bus lines;
- selectively coupling at least some of said digital signals through a first plurality of bidirectional devices to a plurality of conductive columns having a second ordered sequence, each of said columns being coupled to at least one of said data bus lines by one of said bidirectional devices;
- storing said digital signals on at least some of said columns in a plurality of latches, each column being coupled to one of said latches, said column being latched by one of said latches at the stored logical value corresponding to the logical value of said digital signal coupled to said latch;
- and
- selectively coupling an ordered subsequence of said second ordered sequence of columns to said plurality of data bus lines through a second plurality of bidirectional devices, said digital signals on said plurality of data bus lines assuming said ordered subsequence of said columns.
Dependencies are inferred from the claim text.