US 4,051,332 AGranted

Multiplex digital echo suppression system

AssigneeNippon Telegraph & Telephone Public Corporation

InventorsKazuo Izumi, Kazuto Izumi

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Abstract

The invention discloses a multiplex digital echo suppression system in which on each of the transmitting and receiving sides the PCM signal for each channel is converted into the parallel signal and also into the absolute value signal representing the absolute value of the PCM signal by eliminating the sign bit; thus converted signals are accumulated for a predetermined time in a transmitting-side and receiving side accumulators and then compared in a comparator so that the output is derived from the comparator when the accumulated signal in the transmitting-side accumulator is higher in level than the signal accumulated in the receiving-side accumulator; in response to the output signal from the comparator, a first timer is set to a first predetermined time during which the signal is derived from the first timer; when the signal level in the receiving-side accumulator is higher than a predetermined level of a threshold level comparator, the output is derived therefrom and applied to a second timer which in turn is set to a second predetermined time shorter than the time of the first timer, the output signal being derived from the second timer during said second predetermined time. The output from the first timer is applied to a receiving-side logic circuit which in turn controls an attenuator while the outputs from the first and second timers are applied to a transmitting-side logic circuit which controls an echo switch by the logical combination of said output signals.

A multiplex digital echo suppression system comprising

a. a transmitter-side absolute value converter for converting the transmitting-side PCM signal for each channel into a parallel PCM signal with the sign bit eliminated and representing the absolute value of the transmitting-side PCM signal,
b. a receiving-side absolute value converter for converting the receiving-side PCM signal for each channel into a parallel PCM signal with the sign bit eliminated and representing the absolute value of the receiving-side PCM signal,
c. a transmitting-side accumulator and a receiving-side accumulator each for accumulating the output signal from the corresponding absolute value converter for a predetermined time,
d. first comparator means for comparing the output signal of each channel derived from said transmitting-side accumulator in synchronism with the transmitting-side PCM signal with the output signal for the corresponding channel derived from said receiving-side accumulator in synchronism with the receiving-side PCM signal and for generating the output signal when the output from said transmitting-side accumulator is higher than the output from said receiving-side accumulator,
e. first timer means which is set for a first predetermined time in response to the output signal from said first comparator means and continuously generates an output signal during said first predetermined time,
f. second threshold lever comparator means for comparing a predetermined threshold leverl with the output for each channel derived from said receiving-side accumulator and for generating an output signal when the output from said receiving-side accumulator is higher than said predetermined threshold level,
g. second timer means which is set for a second predetermined time shorter than said first predetermined time in response to the output signal from said second comparator means and continuously generates an output signal during said second predetermined time,
h. receiving-side logic circuit means including attenuator means for attenuating the receiving-side input PCM signal in said certain channel in response to the output for said certain channel from said first timer means, and
i. transmitting-side logic circuit means including echo switching means for opening and closing said echo switching means for said certain channel in response to a logical combination of the outputs for said certain channel from said first and second timer means.

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Abstract

Claims5