US 4,050,097 AGranted

Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus

AssigneeHoneywell Information Systems Inc.

InventorsMing T. Miu, Virendra S. Negi, Richard A. Lemay

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Abstract

Data transfer synchronization is achieved in a data processing system by a transferring unit enabling a clock cycle stall mechanism each time a transfer is attempted, disabling such mechanism upon receipt of a predetermined response from the receiving unit, the mechanism actually producing a clock cycle stall if such predetermined response is delayed beyond the duration of the clock cycle. Further, such stall mechanism is enabled in a receiving unit before the expected receipt of information, and actually produces a clock cycle stall if such response is so delayed.

Claims12

Dependent claims

Data transfer apparatus:

A. clock means, having a control input and an output, for providing a stream of clock pulses at said output, said clock means including means for inhibiting the generation of said clock pulses in response to the presence of a stall signal at said control input at a time when one of said clock pulses should have occurred, said stall signal having no effect on the generation of said clock pulses if said stall signal is received after the occurrence of a said clock pulse and is no longer present at a time when a next one of said clock pulses should normally be generated;
B. a plurality of units, including a first unit and a second unit, said clock means included in said first unit;
C. a common electrical bus coupled with each of said units for enabling the transfer of information between said units;
D. means, included in said first unit, for generating a first signal indicating a request for the use of said bus;
E. means for generating a second signal indicating the granting to said first unit of the use of said bus;
F. means, included in said first unit and responsive to said second signal, for transferring information over said bus to said second unit;
G. stall signal generating means, responsive to said first signal and the next occurring one of said clock pulses, for generating a first said stall signal;
H. means for coupling said first said stall signal for receipt by said control input of said clock means;
I. means, included in said second unit and responsive to said information transferred from said first unit, for providing a positive acknowledgement over said bus to said first unit, indicating that said second unit has accepted said information;
J. means, included in said first unit and responsive to said positive acknowledgement, for disabling said stall signal generating means, thereby removing said first said stall signal from said control input;
and
K. means, included in said clock means, for enabling the generation of a said clock pulse in response to the said removal of a said stall signal from said control input.

9 more elements

Dependencies are inferred from the claim text.

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Abstract

Data transfer apparatus:

A. clock means, having a control input and an output, for providing a stream of clock pulses at said output, said clock means including means for inhibiting the generation of said clock pulses in response to the presence of a stall signal at said control input at a time when one of said clock pulses should have occurred, said stall signal having no effect on the generation of said clock pulses if said stall signal is received after the occurrence of a said clock pulse and is no longer present at a time when a next one of said clock pulses should normally be generated;
B. a plurality of units, including a first unit and a second unit, said clock means included in said first unit;
C. a common electrical bus coupled with each of said units for enabling the transfer of information between said units;
D. means, included in said first unit, for generating a first signal indicating a request for the use of said bus;
E. means for generating a second signal indicating the granting to said first unit of the use of said bus;
F. means, included in said first unit and responsive to said second signal, for transferring information over said bus to said second unit;
G. stall signal generating means, responsive to said first signal and the next occurring one of said clock pulses, for generating a first said stall signal;
H. means for coupling said first said stall signal for receipt by said control input of said clock means;
I. means, included in said second unit and responsive to said information transferred from said first unit, for providing a positive acknowledgement over said bus to said first unit, indicating that said second unit has accepted said information;
J. means, included in said first unit and responsive to said positive acknowledgement, for disabling said stall signal generating means, thereby removing said first said stall signal from said control input;
and
K. means, included in said clock means, for enabling the generation of a said clock pulse in response to the said removal of a said stall signal from said control input.

9 more elements