Translator lookahead controls

Abstract

Lookahead circuits for an address relocation translator containing stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory. An additional pair of bit positions are provided with each SR to receive lookahead bits from decoder loading circuits which decode a physical address being loaded into the SR to indicate the storage unit containing the addressed block. During each subsequent address translation, the loaded lookahead bits are outgated while the block address is being read from an SR. The lookahead bits are decoded for selecting the required storage unit component of the main memory, and a translator interface is switched to that unit. The lookahead bits are handled by parallel high-speed circuits which operate faster than the larger translation circuits handling the block address being read from the SR. As a result, the required storage unit is selected before a storage unit cycle is generated by the translator for accessing the addressed block.

Dependencies are inferred from the claim text.