Programmable microwave modulator

A circuit for generating a linear analog signal having a predetermined amplitude pattern and period comprising:

• a. a memory having a plurality of memory address locations for storing digital data;
• b. means for entering digital data into said memory, said digital data determining said amplitude pattern of said linear analog signal;
• c. means for sequentially addressing said memory and sequentially reading out the digital data stored in a predetermined number of memory address locations;
• d. a ripple counter generating a plurality of output signals inputing said memory, said plurality of ripple counter output signals defining the memory address location read out of said memory;
• e. means connected to said ripple counter for generating a series of timed clock pulses having a predetermined period, the period of said clock pulses determining the period of said linear analog signal, each said clock pulse advancing said ripple counter by one;
• thereby sequentially addressing said memory and sequentially reading out the digital data stored in a predetermined number of memory address locations;
• f. means for generating a start-reset pulse;
• g. means for generating a first stop pulse;
• h. a first monostable multivibrator having a first specific time constant associated therewith for generating a first logic one pulse and a first logic zero pulse simultaneously in response to said start-reset pulse;
• i. means connected to said plurality of ripple counter outputs for generating a second stop pulse when said predetermined number of memory address locations have been addressed and read out;
• j. a second monostable multivibrator having a second specific time constant associated therewith for generating a second logic zero pulse in response to said first and second stop pulses, said second time constant being larger than said first time constant;
• k. logic means connected to receive said first logic zero pulse, said first logic one pulse, and said second logic zero pulse for generating a continuous enable signal after receiving said first logic one pulse and said first logic zero pulse, for generating a continuous disable signal after receiving said second logic zero pulse, for generating a temporary disable signal after receiving said first logic one pulse and said first logic zero pulse for the second time without the intervening reception of said second logic zero pulse, said enable signal resetting said ripple counter and enabling said clock means, said disable signal resetting said ripple counter and disabling said clock means;
• l. means connected to said memory for converting the digital data read out of said memory to said linear analog signal.