Equate operand address space control system
AssigneeInternational Business Machines Corporation
InventorsRichard Eugene Birney, Robert Allen Hood
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Abstract
The disclosure describes equate operand spaces (EOS) control over the addressabilities accessed by means of different address keys in an address key register (AKR) in a processor. Executing instructions, and their source and sink type operands may have different address keys in the AKR, and therefore different addressabilities. When enabled, the EOS control forces each source operand fetch to occur within the sink operand addressability specified in the AKR, even though the AKR explicitly contains a different addressability for source operands. When the EOS feature is disabled, the source operand addressability contained in the AKR is used when fetching source operands. An EOS field in the AKR stores whether the EOS state is enabled or disabled in the processor.
Claims6
A system for protecting the contents of main storage of a processor using a plurality of storage protect keys operated by the processor having an equateoperand spaces (EOS) control feature, comprising
- storage access request means in the processor for signalling storage access requests sensed in the processor while fetching and executing instructions,
- means for generating different storage access type signals for different types of storage accesses signalled by the access request means including an instruction access type signal and at least one operand access type signal,
- a plurality of key register sections, each key register section corresponding to an access type gated from the generating means, a key provided in each section being associated with the access type signal connected to the outgate of the respective section,
- key selection means for selecting the outgates of the respective key register sections under control of the respective storage access type signals provided by the generating means,
- an equate-operand-spaces (EOS) latch which is set and reset by execution of predetermined instructions by the processor,
- first means for disabling one key register outgate in response to the setting of the EOS latch, and
- second means for enabling another outgate in response to activation of the storage access type signal connected to the one outgate when the EOS latch is set,
- whereby when the EOS latch is set, the another outgate selects the key contained in another key register section instead of the key in the key register section associated with the one outgate;
- but when the EOS latch is reset, the one outgate being enabled to select the key in the associated key section.
A protected storage system having the EOS control feature as defined in claim 8, further comprising
- I/o subchannels connected to the processor, each I/O subchannel having a cycle steal (CS) key register section for storing an assigned CS key, each I/O subchannel outputting a CS register section when it outputs a CS storage access request signal,
- the key selection circuit means also having inputs receiving the CS key register output,
- the priority circuit means providing highest output priority to the CS key register output when a CS storage request signal is received.
Dependencies are inferred from the claim text.