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US 4,050,058 AGranted
Microprocessor with parallel operation
AssigneeXerox Corporation
InventorRichard A. Garlic
Life of this patent
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Abstract
A highly parallel microprocessor using a logic gating structure and a microinstruction organization which permits direct access by each of the microprocessor components to a tri-bus system. Operation is defined by a single phase clock, during which all portions of a microinstruction are executed. The system further permits overlap operation for microprocessor instructions, thereby allowing for the fetching of a next instruction while executing a current instruction. The use of general purpose, non-dedicated registers is contemplated, thereby to avoid the need for multi-phase clocking.
Claims10
A microprocessor comprising:
- a. a control memory for storing control words,
- b. a clock for generating a train of clock signals,
- c. a first bus,
- d. a second bus,
- e. means connecting said first bus and said second bus,
- f. a plurality of sources of data,
- g. a plurality of destinations for storing data,
- h. first selecting means for selecting one of said plurality of sources of data,
- i. placing means for placing data from said selected source on said first bus,
- j. said connecting means comprising transferring means for transferring data from said first bus to said second bus,
- k. second selecting means for selecting one of said plurality of destinations for said data,
- l. storing means for storing data in said selected destination, and
- m. decoder means responsive to one of said control words and to a single one of said clock signals for simultaneously activating:
- 1. said first selecting means thereby selecting one of said plurality of sources of data,
- 2. said placing means thereby placing data from said selected source on said first bus,
- 3. said transferring means thereby transferring said data from said first bus to said second bus,
- 4. said second selecting means thereby selecting one of said destinations for said data, and
- 5. said storing means thereby storing said data on said second bus in said selected destinations whereby highly parallel operation of said microprocessor is enabled during a single clock cycle by said simultaneous activation of said first and second selecting means, said placing, transferring and storing means by said decoder means.
15 more elements
A microprocessor comprising:
- a control memory for storing control words, a clock for generating a train of clock signals, a first bus a second bus, and a third bus, sources of data connectable to said first and third bus, a destination for storing data connectable to said second bus, arithmetic and logic means connected with inputs from said first and third buses and an output to said second bus, a function generator connected with means for providing inputs from said first and third buses and means for providing output to said second bus, and means responsive to one of said control words and to a single one of said clock signals for simultaneously generating:
- a. a first signal to activate means for selecting a source of data for connection to said first bus,
- b. a second signal to activate means for selecting a source of data for connection to said third bus,
- c. a third signal to activate means for placing data on said first bus and said third bus from their respective sources,
- d. a fourth signal to activate means for selectively electrically disconnecting said arithmetic and logic unit from said first, second, and third buses,
- e. a fifth signal to activate means for selectively electrically connecting said function generator to siad first, second, and third buses, said function generator operating on said data on said first and third buses and placing the result of said operation of said second bus, and
- f. a sixth signal to activate means for placing said result in a destination selected and connected to said second bus.
4 more elements
Dependencies are inferred from the claim text.