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US 4,050,030 AGranted
Offset adjustment circuit
AssigneeNational Semiconductor Corporation
InventorRonald W. Russell
Life of this patent
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AssigneeNational Semiconductor Corporation
InventorRonald W. Russell
Estimating the term…
An offset adjustment circuit for a differential amplifier includes a current source connected in series with a resistor for establishing a biasing voltage for a pair of field effect transistors (FET) having variable resistors in their biasing circuits. These FET's are connected to introduce currents respective connections between an input stage and a second stage of the differential amplifier. The difference of the currents supplied by the FET's divided by the transconductance of the input stage of the differential amplifier corresponds to an offset which remains fixed with changes in temperature. The offset introduced by the FET's, as determined by the adjusted values of the resistors in their biasing circuits, may be in opposition to the offset of the differential amplifier to either reduce it partially or completely, or it may be additive to the offset of the differential amplifier, as desired.
In combination with a differential amplifier including an input stage and a second stage connected together by a pair of output lines having an offset error voltage, an offset voltage adjusting circuit, comprising:
Dependencies are inferred from the claim text.