US 4,049,979 AGranted

Multi-bootstrap driver circuit

AssigneeNational Semiconductor Corporation

InventorsMark S. D. Shieu, Robert B. Johnson, Ronald C. Laugesen

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Abstract

Plural bootstrap capacitors are coupled to an output stage of a MOSFET driver. A conventional bootstrap driver is preceded by one or more additional bootstrap stages. Each one includes a capacitor, a tri state inverter and a delay section. When the output stage is off all capacitors are discharged. To turn the output stage on, all capacitors, including the output gate capacitance, are charged in parallel. Then each capacitor in turn is caused to pump its charge into the gate of the output stage, with the last capacitor pumping the output stage gate voltage to a level well in excess of the applied power supply voltage.

Claims8

Dependent claims

A FET output stage driver, said driver employing plural bootstrap means and having the capability of applying a gate electrode drive signal having an amplitude substantially in excess of the supply potential of said output stage, said driver being coupled to the gate electrode of said output stage FET and comprising:

first and second coupling capacitors, each capacitor having two electrodes, one of which is coupled to said output stage gate electrode;
a first tri state FET inverter having an input terminal, an output terminal, and a control terminal, said input terminal being coupled to signal input terminal said output terminal being coupled to said output stage gate electrode;
a FET delay buffer having an input terminal, and output terminal, and a signal delay characteristic such that the signal appearing at said output appears after a first delay interval following an applied input signal, said input terminal being coupled to said signal input terminal, and said output terminal being coupled to said control terminal of said first tri state inverter, whereby said first tri state inverter will respond to an input signal and act as an inverter for the duration of said first delay interval after which said output terminal is rendered floating;
a second tri state FET inverter having an input terminal, an output terminal, and a control terminal, said input terminal being coupled to said output terminal of said delay buffer, and said output terminal being coupled to said second terminal of said first capacitor,
a FET delay inverter having an input terminal, an output terminal, and a signal delay characteristic such that the signal appearing at said output appears after a second delay interval following an applied input signal, said input terminal being coupled to said output terminal of said second tri state inverter and said output terminal being coupled to said control terminal of said second tri state inverter whereby said second tri state inverter will respond to an input signal and act as an inverter for the duration of said second delay interval after which said output terminal is rendered floating;
and
a FET inverter having an input terminal and an output terminal, said input terminal being coupled to said output terminal of said delay inverter and said output terminal being coupled to said second terminal of said second capacitor, whereby said first and said second capacitors along with the gate capacitance of said FET output stage all become discharged to V.sub.SS when said first tri state inverter input terminal is at logic one signal state, said plurality of capacitors along with said gate capacitance of said FET output stage all charge to a substantial fraction of V.sub.DD during said first delay interval after which said input terminal of said first tri state inverter is switched to logic zero state, second capacitor along with said gate capacitance of said FET output stage both charge to a potential that is a substantial fraction of twice V.sub.DD during said second delay interval, and said gate capacitance of said FET output stage charges to substantially in excess of twice V.sub.DD after said second delay interval.

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Dependencies are inferred from the claim text.

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Abstract

first and second coupling capacitors, each capacitor having two electrodes, one of which is coupled to said output stage gate electrode;
a first tri state FET inverter having an input terminal, an output terminal, and a control terminal, said input terminal being coupled to signal input terminal said output terminal being coupled to said output stage gate electrode;
a FET delay buffer having an input terminal, and output terminal, and a signal delay characteristic such that the signal appearing at said output appears after a first delay interval following an applied input signal, said input terminal being coupled to said signal input terminal, and said output terminal being coupled to said control terminal of said first tri state inverter, whereby said first tri state inverter will respond to an input signal and act as an inverter for the duration of said first delay interval after which said output terminal is rendered floating;
a second tri state FET inverter having an input terminal, an output terminal, and a control terminal, said input terminal being coupled to said output terminal of said delay buffer, and said output terminal being coupled to said second terminal of said first capacitor,
a FET delay inverter having an input terminal, an output terminal, and a signal delay characteristic such that the signal appearing at said output appears after a second delay interval following an applied input signal, said input terminal being coupled to said output terminal of said second tri state inverter and said output terminal being coupled to said control terminal of said second tri state inverter whereby said second tri state inverter will respond to an input signal and act as an inverter for the duration of said second delay interval after which said output terminal is rendered floating;
and
a FET inverter having an input terminal and an output terminal, said input terminal being coupled to said output terminal of said delay inverter and said output terminal being coupled to said second terminal of said second capacitor, whereby said first and said second capacitors along with the gate capacitance of said FET output stage all become discharged to V.sub.SS when said first tri state inverter input terminal is at logic one signal state, said plurality of capacitors along with said gate capacitance of said FET output stage all charge to a substantial fraction of V.sub.DD during said first delay interval after which said input terminal of said first tri state inverter is switched to logic zero state, second capacitor along with said gate capacitance of said FET output stage both charge to a potential that is a substantial fraction of twice V.sub.DD during said second delay interval, and said gate capacitance of said FET output stage charges to substantially in excess of twice V.sub.DD after said second delay interval.

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