US 4,049,975 AGranted

Transistor circuits

AssigneeFerranti Limited

InventorStephen Francis Colaco

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Abstract

In a non-gold-doped TTL device to be energized by a potential supply of at least 4.5 volts; the charge carrier concentration within a NPN multi-emitter input transistor is reduced by connecting together the base and the collector; undesirable emitter-to-emitter transistor action is prevented, by reducing the inverse current gain factor of the input transistor, and preventing this transistor from saturating, by providing a diode within the phase splitter stage, to ensure that the input threshold level of the device is at least two forward biased diode potentials above the least positive supply rail; and providing a suitable pull-up stage for the output transistor, which pull-up stage may comprise a modified Darlington pair of transistors, including a resistor between the emitter of the first transistor and the base of the second transistor, and a resistor between the base and the emitter of the second transistor.

Claims6

Dependent claims

A transistor-transistor logic circuit arrangement having NPN transistors, and to be energised by a potential supply of at least 4.5 volts, including a multi-emitter input transistor, having an emitter individually connected to each required input for the circuit arrangement, the base is connected via a resistor to a first rail to be maintained at a first, finite positive potential level, the collector is connected to the base to reduce, in the operation of the circuit arrangement, the concentration of stored charge carriers within the transistor, and the collector is also connected to a phase splitter stage connected between the first rail and a second rail to be maintained at a second potential level, less positive than the potential level of the first rail, a diode is provided within the phase splitter stage, and is connected between the input transistor and the second rail to ensure that the input threshold level of the circuit arrangement is above the potential level of the second rail by substantially the maximum obtainable potential difference across two forward biased diodes, one output of the phase splitter stage is connected to the base of an output transistor for the circuit arrangement, the emitter of the output transistor is connected to the second rail, and the other output of the phase splitter stage is connected to a pull-up stage for the output transistor.

A non-gold-doped transistor-transistor logic circuit device has at least partially embodied in a monolithic semiconductor body a circuit arrangement having NPN transistors, and to be energised by a potential supply of at least 4.5 volts, including a multi-emitter input transistor, having an emitter individually connected to each required input for the circuit arrangement, the base is connected via a resistor to a first rail to be maintained at a first, finite positive level, the collector is connected to the base to reduce, in the operation of the circuit arrangement, the concentration of stored charge carriers within the transistor, and the collector is also connected to a phase splitter stage connected between the first rail and a second rail to be maintained at a second potential level, less positive than the potential level of the first rail, a diode is provided within the phase splitter stage, and is connected between the input transistor and the second rail to ensure that the input threshold level of the circuit arrangement is above the potential level of the second rail by substantially the maximum obtainable potential difference across two forward biased diodes, one output of the phase splitter stage is connected to the base of an output transistor for the circuit arrangement, the emitter of the output transistor is connected to the second rail, and the other output of the phase splitter stage is connected to a pull-up stage for the output transistor.

Dependencies are inferred from the claim text.