Precharge arithmetic logic unit
AssigneeTexas Instruments Incorporated
InventorsGary W. Boone, Jerry L. Vandierendonck
Life of this patent
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Abstract
A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes, on a single chip, an arithmetic logic unit (ALU), an instruction register, a random access memory and a control system. Interconnection of the functional elements of the CPU is accomplished via sequential use of a common parallel buss. The ALU contains precharged parity and carry propagate circuits which enhance circuit speed. The precharged circuits are formed using conventional insulated-gate-field-effect transistor fabrication techniques.
Claims6
A circuit for determining the parity between a plurality of logic signals comprising:
- a. first pair of series connected field effect transistors connected between a first node and a first clock voltage source, said transistor having gates for receiving logic signals, and means for applying a first logic signal and the complement of a second logic signal to the gates of the field effect transistors, respectively;
- b. a second pair of series connected field effect transistors connected between said first node and said first clock source, said second pair of transistors having gates for receiving logic signals, and means for applying the complement of said first logic signal and said second logic signal to the gates of the second pair, respectively;
- and
- c. means for precharging said first node to a reference negative voltage simultaneously with applying said first and second signals whereby when said first and second signals are of opposite logic levels said node is discharged thereby producing at said node a logic 1 level corresponding to uneven parity.
A circuit for determining the parity between a plurality of logic signals comprising:
- a. first pair of series connected field effect transistors connected between a first node and a first clock voltage source, said transistors respectively having gates for receiving a first logic signal and the complement of a second logic signal;
- b. a second pair of series connected field effect transistors connected between said first node and said first clock source, said second pair of transistors respectively having gates for receiving the complement of said first logic signal and said second logic signal;
- c. means for precharging said first node to a reference negative voltage simultaneously with applying said first and second signals whereby when said first and second signals are of opposite logic levels said node is discharged, thereby producing at said node a logic 1 level corresponding to uneven parity, said means for precharging said first node including a field effect transistor connected between said node and said reference negative voltage, the gate electrode of said transistor being connected to said first clock voltage source;
- d. a third pair of series connected field effect transistors connected between a second node and said first clock source, respectively having gates for receiving said first and second logic signals;
- e. fourth pair of series connected field effect transistors connected between said second node and said first clock source, respectively having gates for receiving the complement of said first and second logic signals;
- and
- f. means for precharging said second node to a reference negative voltage simultaneously with applying said first and second signals whereby when said first and second signals are of like logic levels said second node is discharged producing at said second node a logic 1 level corresponding to even parity.
Dependencies are inferred from the claim text.