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AssigneeCSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
InventorWouter Martinus Dirk Van Veen
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A read/write memory of n stages, periodically addressed in a recurrent scanning cycle of n time slots in which binary words are written in and read out from respective stages, is connected to a data-handling network by way of a writing multiple and a reading multiple each traversing a respective selective inverter, i.e., an upstream inverter in the writing multiple and a downstream inverter in the reading multiple. The two inverters are controlled by a generator of pseudo-random binary signals, unrelated to those processed in the data-handling network, having an operating cycle coextensive with a scanning cycle. Depending on the character of the control signals issuing from this pseudo-random generator during each cycle, the two selective inverters pass the bits of their incoming words either in their original or in a complemented form; with words written in a memory stage in one cycle read out in the immediately following cycle, the control signals delivered to the two inverters are identical but staggered by one cycle so that the words appearing in the output of the downstream inverter match those fed into the upstream inverter in the preceding cycle when the memory operates properly. Under certain circumstances, when a memory stage is addressed out of turn so that loading and reading of its contents occur successively in the same cycle, the staggering of the two control signals is canceled. Malfunctions of the memory are detected by parity checks carried out on the words traveling along the reading multiple to the downstream inverter; an alarm signal is emitted upon the occurrence of an error in the same bit position in two consecutive cycles.
A method of testing the performance of a multistage memory whose stages are periodically addressed in respective time slots of a recurrent scanning cycle, each time slot being divided into a reading phase and a writing phase, for inscribing an incoming multibit data word in an addressed memory stage during a writing phase and retrieving an inscribed data word from an addressed memory stage during a reading phase of any time slot, comprising the steps of:
In a data-handling system, in combination:
Dependencies are inferred from the claim text.