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US 4,048,712 AGranted
Processes for manufacturing semiconductor devices
AssigneeSelenia Industrie Elettroniche Associate S.p.A.
InventorMarina Buiatti
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Abstract
A process for manufacturing MES-FET transistors with self-aligned Schottky barrier gate electrode, in which a layer of metal is deposited on a semiconductor slice, a resist geometry corresponding to the spacing of the drain and source ohmic contacts is defined, the excess metal is etched away with controlled underetching under said resist, a metal is then evaporated for forming the ohmic contacts, the metal remaining after said etching constituting the self-aligned gate electrode.
Claims4
A process of manufacturing a field effect transistor having a Schottky barrier gate electrode, comprising the steps of
- providing a substrate of semiconductor material,
- depositing on the exposed surface of said substrate a first metal layer, a part of which will form the Schottky junction gate electrode,
- applying on said metal layer a strip of photo-resist having a width greater than the final width of said gate electrode and corresponding to the desired spacing between two ohmic contacts of said field effect transistor,
- chemically etching said first metal layer to obtain a desired underetching with respect to said photo-resist strip,
- applying a second metal layer to said substrate by an evaporation process to form said ohmic contacts, the edges of said contacts being defined with precision by the edges of said resist strip,
- and removing said photo-resist strip from said gate electrode and alloying said ohmic contacts.
3 more elements
Dependencies are inferred from the claim text.