US 4,048,673 AGranted

CPU - I/O bus interface for a data processing system

AssigneeData General Corporation

InventorsGardner Cox Hendrie, Harold Springer Crafts

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Abstract

There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or interfacing means for interfacing with I/O means (bus structure). The I/O means includes improved CPU transceiver and peripheral device ransceiver apparatus. The device transceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU transceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data transmission means which maintains accurate processing of data regardless of propagation delay, distortion, data skewing, etc., due to varying transmission distances and inherent limitations of MOS, bipolar, and other technology.

Claims10

Dependent claims

In a data processing system including (a) CPU with digital circuitry, (b) a main memory interfacing with said CPU, (c) I/O means for connecting between said CPU and peripheral devices, and (d) a clock source, interface means contained within said CPU for interfacing with said I/O means, said interface means comprising:

means for receiving pulses derived from said clock source and for deriving further pulses therefrom;
means for normally establishing an input mode of said interface means and responsive to signals from said CPU for establishing an output mode of said interface means;
a first I/O pad connected to said I/O means;
first shift register means for (1) serially receiving a first byte of a two byte data word from said first I/O pad responsive to certain of said further derived pulses and to the operation of said establishing means establishing said input mode and (2) serially generating said first byte of another two byte data word onto said first I/O pad responsive to other of said further derived pulses and to the operation of said establishing means establishing said output mode;
a second I/O pad connected to said I/O means;
second shift register means for (1) serially receiving the second byte of said two byte data word from said second I/O pad responsive to said certain of said further derived pulses and to the operation of said establishing means establishing said input mode and (2) serially generating said second byte of said another data word onto said second I/O pad responsive to said other of said further derived pulses and to the operation of said establishing means establishing said output mode;
and
means for parallel transferring (1) said data word from said first and second shift register means to said digital circuitry and (2) said another data word from said digital circuitry to said first and second shift register means.

5 more elements

Dependencies are inferred from the claim text.