Memory device
AssigneeHoneywell Information Systems Inc.
InventorDarrell L. Fett
Life of this patent
Estimating the term…
Abstract
A READ ONLY memory is disclosed wherein the bits of a given word are separately stored in a number of individual storage arrays. The individual storage arrays each contain a plurality of addressable bit storage locations. These bit storage locations are first accessed and thereafter sensed in response to a given address. The accessing and sensing is implemented by current mode logic in a manner which effectively develops and thereafter utilizes various current paths.
Claims23
A data storage system for accessing stored words consisting of n-bits of information, said system comprising:
- a plurality of means for storing each of the n-bits of information;
- means for receiving an address identifying the location of each of the n-bits of information in each of said plurality of storage means;
- means for selectively developing current paths through each of said plurality of storage means in response to said received address;
- said means for selectively developing current paths further comprising:
- means for applying a first electrical potential upstream of the particular addressed storage location within said storage means;
- means for applying a second electrical potential downstream of the particular addressed storage location within said storage means, said second electrical potential being lower than said first electrical potential so as to establish a current path through said particular addressed location;
- said means for applying a first electrical potential upstream of the particular addressed storage location still further comprising:
- a plurality of means for providing current from said first electrical potential to each of said storage means;
- said plurality of means for providing current from said first electrical potential to each of said storage means comprising:
- a plurality of conductive lines, each being conductively connected to said storage means;
- means for sensing each of said plurality of storage means to ascertain the conductive status of the selectively developed current path therein;
- each of said storage means comprising:
- a plurality of multi-emitter transistors each with a base being connected to one of said plurality of conductive lines;
- each of said storage means further comprising:
- a plurality of emitter lines each of which is conductively closed with respect to at least one of the emitters of said multi-emitter transistors.
In a data storage device wherein data bits are electronically stored in a matrix array having bit storage locations therein defined by a first address and a second address, apparatus for accessing and sensing the stored bits said apparatus comprising:
- a plurality of current source means for providing electrical current to said bit storage locations;
- means, responsive to the first address, for drawing current from said plurality of current source means so as to deactivate all but one of said plurality of current source means;
- a plurality of means for drawing current from said bit storage locations;
- means, responsive to the second address, for selectively activating one of said plurality of means for drawing current from said bit storage locations;
- and
- means for sensing the conductive status of the bit storage location having both the first and second addresses;
- said first and second addresses each further comprising a plurality of bi-level address signals each of which corresponds to a particular bit of one of said first and second addresses and said means responsive to said first address for drawing current from said current source means comprises:
- means, connected to at least two different current source means and being responsive to a particular bi-level address signal, for drawing current from only one of said two current source means depending on the signal level of said bi-level signal.
Dependencies are inferred from the claim text.