Programmable sequence controller
AssigneeToyoda Koki Kabushiki Kaisha
InventorToshihiko Yomogida
Life of this patent
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Abstract
In a programmable sequence controller, a logic operation circuit has first and second AND gates, first and second OR gates and first to fourth flip flops. An input is applied to the two AND gates and the two OR gates. The first and second AND gates receive outputs of the first and second flip flops wich receive outputs of the first and second AND gates and are triggered in response to first and second control commands, respectively. The first and second OR gates receive outputs of the third and fourth flip flops which receive outputs of the first and second OR gates and are triggered in response to third and fourth control commands, respectively. A sequence control is performed in response to the outputs of the first to fourth flip flops.
Claims7
A programmable sequence controller comprising:
- memory means for memorizing a sequence program comprising a train of instructions identified respectively by memory addresses thereof, each of said instructions having command information and address information therein, said command information being selected from a group of control commands including a first control command for examining whether an input is in an ON state under the condition of being ANDed with another input, a second control command for examining whether an input is in an OFF state under the condition of being ANDed with another input, a third control command for examining whether an input is in an ON state under the condition of being ORed with another input, and a fourth control command for examining whether an input is in an OFF state under the condition of being ORed with another input,
- an input circuit operatively connected to a plurality of addressed external input devices for converting states of said external input devices into logical values;
- an output circuit operatively connected to a plurality of addressed external output devices to be energized or deenergized;
- a logic operation circuit operatively connected to said memory means and to said input and output circuits;
- means for reading out and feeding said train of instructions from said memory means to said logic operation circuit;
- said logic operation circuit comprising:
- a line connected to receive a logical value of one of said external input devices specified by the address information;
- a first AND gate;
- a first flip flop connected to receive an output of said first AND gate and triggered when said first control command is applied;
- said first AND gate being connected to said line and to receive an output of said first flip flop;
- a second AND gate;
- a second flip flop connected to receive an output of said second AND gate and triggered when said second control command is applied;
- said second AND gate being connected to said line and to receive an output of said second flip flop;
- a first OR gate;
- a third flip flop connected to receive an output of said first OR gate and triggered when said third control command is applied;
- said first OR gate being connected to said line and to receive an output of said third flip flop;
- a second OR gate;
- a fourth flip flop connected to receive an output of said second OR gate and triggered when said fourth control command is applied;
- said second OR gate being connected to said line and to receive an output of said fourth flip flop;
- said first to fourth flip flops being set when triggered and receiving a ONE signal;
- and
- said output circuit being operable to energize or deenergize one of said addressed external output devices in response to the outputs of said first to fourth flip flops.
Dependencies are inferred from the claim text.