Automated character recognition system

A character recognition system, which comprises:

• a. data lift means for scanning a printed character and forming a character image;
• b. analyzer means in electrical communication with said data lift means for scanning said character image by rows and columns in a certain predetermined order to detect horizontal and vertical primary features;
• c. horizontal analyzing means receiving said horizontal primary features in said order for assigning a horizontal classification code in said order to each of said rows according to the size, number and position of horizontal character segments detected within each of said rows, and forming secondary horizontal features based upon the relative position of each horizontal classification code within said order;
• d. vertical analyzing means receiving said vertical primary features in said order for assigning vertical classification codes in said order to each of said columns according to the size and number of vertical character segments detected within each column and forming secondary vertical features based upon the relative position of each vertical classification code within said order;
• and
• e. sequential logic decision means in electrical communication with said horizontal analyzing means and said vertical analyzing means for sequentially testing said secondary horizontal features and said secondary vertical features to identify said printed character.

A system for recognizing a string of characters printed in plural fonts of unknown order, which comprises:

• a. video data lift means for scanning said string of characters and forming character images thereof;
• b. image scan means in electrical communication with said video data lift means for scanning one character image of said character images horizontally and vertically by rows and columns, respectively, to detect primary features including the number of character segments in each of said rows and columns, the segment length and rightmost segment coordinate for each row of said rows having a single character segment, and the segment length for each column of said columns having a single character segment;
• c. feature generation means receiving said primary features for assigning classifications to each row and column of said one character image, and form the order of occurrence of said classifications forming secondary features including the order of detection of said character segments, the number of said character segments detected, and the weight to be accorded said character segments in the identification of one of said string of characters;
• and
• d. sequential logic decision means responsive to said secondary features for identifying one of said string of characters.

In a character recognition system where an image forming means scans a printed character and forms a character image thereof and an analyzer scans said character image horizontally and vertically to detect primary features of said character, the combination which comprises:

• a. first multiplexer means in electrical communication with said analyzer for singularly selecting said primary features and secondary features formed from said primary features;
• b. logic compare means connected to the output of said multiplexer means for comparing said primary features and said secondary features with data fields of stored processing instructions;
• c. reset logic means in electrical communication with said image forming means and said analyzer means for providing status indications therefrom;
• d. logic control means having inputs connected to the outputs of said logic compare means an said reset logic means for indicating a skip instruction condition;
• e. address control means responsive to said logic control means for controlling the addressing of said processing instructions;
• f. address register means responsive to said address control means for selecting said processing instructions;
• g. ROM means responsive to said address register means for providing said processing instructions to said address register means, said logic control means, said reset logic means, said logic compare means and said first multiplexer means;
• h. instruction decoding means in electrical communication with said ROM means for decoding said processing instructions and indicating the identity of said processing instructions to said reset logic means and said address control means;
• i. a feature address register responsive to said instruction decoder means and receiving secondary feature addresses for selecting said secondary features;
• j. RAM means responsive to said feature address register and said instruction decoding means for providing said secondary features;
• k. arithmetic means receiving said secondary features from said RAM means and said processing instructions from said ROM means for modifying said secondary features;
• l. an adder having one input connected to the output of said arithmetic means and a second input connected to the output of said ROM means for providing said secondary feature addresses;
• m. logic OR means having one input connected to the output of said adder for performing a logical OR operation;
• n. feature data register means responsive to said instruction decoding means and receiving the output of said logic OR means for supplying said secondary features to said RAM means;
• o. second multiplexer means responsive to said instruction decoding means and having one input connected to the output of said feature data register means and a second input connected to a logic reference for providing a second input to said logic OR means;
• and
• p. character identification register means responsive to said instruction decoding means and in electrical communication with said ROM means for indicating a character decision.