Solid state break-before-make base module and associated contact elements

#This invention relates generally to solid state relay elements having break-before-make functions and it relates specifically to elements of the preceding type utilizing two transistors in a base module where various kinds of plug-in modules may be utilized on the same base module.

#Solid state relays are known. In the past solid state relay modules have been provided which have on-time delays and off-time delays. In addition in the past, solid state relay modules have been provided which performed time-delayed functions in the making and breaking operation. However, in the past the break-before-make function did not reverse itself when comparing the closing operation and the opening operation; that is, if a device broke before it made on the closing operation, it also broke before it on made on or made the opening operation in the same relay or made. Sometimes, it is desirous that one circuit is not on at any time that another circuit is also on. In order to accomplish that a bracketing break-before-make operation is required; that is, the first circuit should be broken before the second circuit is energized and the second circuit should be de-energized before the first circuit is re-energized. It would be even more advantageous if this break-before-make bracketing function or operation could be accomplished on multiple contacts with synchronous break-before-make operations on all of the multiple contacts. It would be advantageous if the break-before-make bracketing function could be utilized with on-delay and off-delay contact modules.

#In accordance with the invention apparatus is taught which teaches bracketing break-before-make solid state relay apparatus. A unitary power supply or input circuit is provided with translates the starting signal to multiple output circuits, each of which provides synchronous break-before-make operations. In the preferred embodiment there are four synchronous output circuits for every input circuit in a commercial module. In addition, the input signal is provided by a relay operation. The relay operation is of the solid state nature. This allows for cascading or ganging of relay circuitry. Two of the output modules may be utilized to drive an on-time delay module which provides an incremental delay between the time the input relay is energized until the time the output contacts change state. In a preferred embodiment, the output contacts are complementary, that is as one set of contacts opens the other closes. In addition, the bracketing bread-before-make function works at either end of the opening and closing operation. In another embodiment, an off-time delay apparatus is provided that turns on with a break-before-make operation and turns off after the input relay contact has been deenergized with a bracketing break-before-make operation and after a predetermined time delay. Non-time delay modules are provided which merely open and close in a break-before-make operation. No feedback is necessary between the latter elements except for transfer of intelligence in the output circuit of the base module.

#For a better understanding of the invention, reference may be had to the preferred embodiments shown herein in the accompanying drawings in which:

#FIG. 1 shows a four output base module for a solid state relay;

#FIG. 2 shows a schematic diagram of a dual function (NOK/NCK) normally opened or normally closed contact module;

#Referring now to the drawings and FIG. 1 in particular, a base module BM for a solid state relay is shown. In this embodiment the base module BM comprises a unitary input circuit IS and four synchronously operable output circuits OS(1), OS(2), OS(3) and 0S(4). The input terminals for the input stage IS are interconnectable with a source of alternating electrical current S and a series connected relay contact or similar signalling means RC such as pushbutton, etc. The upper end of the relay RC is connected concurrently to the upper side of a primary winding P1 of a transformer T1 and to the anode of a diode D4. The lower end of the relay contact is connected to the upper side of the previously described source S which may be a 120 volt alternating current power supply. The lower side of the source S is connected concurrently to one end of a resistive element R1 to one input terminal of a solid state contact SSC1. The latter connection is made between the cathode of a diode D1 and the anode of a Zener diode ZD1. The other end of the resistive element R1 is connected to one end of a capacitive element C1. The other end of the capacitive element C1 is connected to the other side of the primary winding P1 and to the other input terminal of the solid state contact SSC1. The latter connection is made at the junction between the cathode of a diode D2 and the anode of a Zener diode ZD2. The regulating terminals or cathodes of the latter Zener diodes ZD1 and ZD2 are connected together at the regulating terminal of a third Zener diode ZD3 and at the anode of a light emitting diode LED1. The cathode of the light emitting diode LED1 and the anode of the Zener diode ZD3 are connected together at the anode of a silicon controlled rectifier or similar gated means SCR1. The cathode of the previously mentioned diode D4 is connected to one side of a resistive element R5, the other side of which is connected concurrently to the anode of a diode D3 and to one side of a resistive element R6. The cathode of the diode D3 is connected concurrently to the regulating terminal of a Zener diode ZD5, one side of a capacitive element C3 and one end of a resistive element R4. The other end of the resistive element R4 is connected concurrently to one side of a resistive element R3 and to the regulating terminal of a Zener diode ZD4. The anode of the Zener diode ZD4 is connected concurrently to one side of a capacitive element C2, to one end of a resistive means R2, and to the gate of the previously described silicon controlled rectifier SCR1. The other ends of the previously mentioned diodes D1 and D2, as well as the other ends of the previously mentioned resistive elements R2, R3 and R6, and the other ends of the capacitive elements C2 and C3, and the other end of the Zener diode element ZD5, are connected together and to the cathode of the silicon controlled rectifier SCR1.

#The transformer T1 has in the preferred embodiment of the invention four generally identical secondary windings S1A S1B, S1C and S1D. The secondary winding S1A drives an output stage OS(1), the secondary winding S1B drives an output state (OS(2), the secondary winding S1C drives an output stage OS(3), and the secondary winding S1D drives an output stage OS(4). Each of the previously described output stages OS(1) through OS(4) has five outputs. The first output is designated the X output, the second output is designated the YA output, the third output is designated the YB output, the fourth output is designated the ZA output and the fifth output is designated the ZB output. The particular output stage in question is identified in each case by a number in parentheses behind the appropriate letter. As an example, the output stage OS(3) has an X(3) output, the output stage OS(4) has a YB(4) output and the output stage OS(1) has an output terminal ZB(1).

#The operation of the output stages are generally similar and identical and simultaneous with regard to the application and removal of energy from the primary winding P1 of the transformer T1. Since the output stages are identical, the electrical interconnection of the elements and the description of the elements for only one of them will be described, it being understood that the others are essentially the same. The output stage OS(2) comprises a diode bridge DB1 connected across the output terminals of the secondary winding S1B. Connected across the output windings of the diode bridge DB1 are the elements of the output stage O(2). There is connected to the positive output winding one side of a resistive element R7a and the anode of a diode element D5. The other side of the resistive element R7a is connected concurrently to one side of a capacitive element C5, to one side of a resistive element R8, and to the emitter of a transistor Q2. The base of the transistor Q2 is connected to the other side of the resistive element R8 and to one side of a resistive element R9, the other side of which is connected to the negative output terminal of the bridge DB1. The collector of the transistor Q2 is connected to one side of a resistive element R11, the other side of which represents the X(2) terminal of the output stage OS(2). The other side of the previously mentioned capacitive element C5 is also connected to the negative or return terminal of the bridge DB1. The other side of the cathode of the diode D5 is connected concurrently to one side of a capacitive element C4 and to one side of a resistive element R7. The other side of the resistive element R7 is connected to one side of a resistive element R10 and to the base of a transistor Q1. The collector of the transistor Q1 represents the YA(2) and YB(2) output terminals of the output stage OS(2). The emitter of the transistor Q1, the other side of the resistive element R10 and the other side of a capacitive element C4 are also tied together and connected to the return or negative side of the diode bridge DB1. This latter point also represents the two output terminals ZA(2) and ZB(2) for the output stage OS(2).