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US 4,048,518 AGranted
MOS buffer circuit
AssigneeIntel Corporation
InventorJames T. Koo
Life of this patent
Estimating the term…
Abstract
An MOS buffer circuit particularly suitable as an input stage for receiving a lower level input signal in an MOS integrated circuit. A transistor is employed to decouple an input transistor from a load, thereby allowing an output signal from the circuit to rise more quickly.
Claims3
In an MOS inverter which includes an input transistor coupled in series with a load means, an improvement comprising:
- a decoupling transistor coupled between said load means and said input transistor;
- the gate of said decoupling transistor being coupled to a controlled variable potential means for controlling the gate potential of said decoupling transistor in response to a change of voltage on the gate of said input transistor;
- whereby the voltage changes on the respective gates of said input transistor and said decoupling transistor together cause said decoupling transistor to rapidly decouple said input transistor from said load means, thereby allowing the output signal from said inverter to charge more quickly.
An MOS circuit for providing an output signal in response to an input signal comprising:
- load means coupled to a source of potential;
- a decoupling transistor coupled to said load means;
- an input transistor coupled to said decoupling transistor, the gate of said input transistor being coupled to receive said input signal;
- and,
- control means for controlling the potential on the gate of said decoupling transistor comprising, a first transistor having its gate coupled to the common terminal between said input transistor and said decoupling transistor, and one of its terminals coupled to said gate of said decoupling transistor;
- whereby said decoupling transistor decoupled capacitance associated with said input transistor thereby permitting said output signal of said circuit to rise more quickly.
3 more elements
Dependencies are inferred from the claim text.