Digital phase-locked loop for speed measurement, in particular for use in antiskid control systems

A digital phase-locked loop for speed measurement, in particular for use in antiskid control systems, for the conversion of the frequency of an input pulse sequence which is proportional to the speed of a rotatable member into a digital numerical value suitable for use in a digital arithmetic unit including:

• input means for providing a certain numerical value which will always be the same and which is allocated to any input pulse sequence;
• at least one adder means having at least three inputs thereto and at least one output, one of said inputs of said adder being connected to said input means;
• first storage register means having one input connected to and receiving the output of said first adder means, having at least another input for receiving clock pulses;
• means for generating clock pulses;
• detector means having a selected predetermined upper limit and a predetermined lower limit having one input connected to the output of said first storage register means, said detector means having another input connected to said means for generating clock pulses and generating at regular intervals a positive digital output numerical value when the content of said first storage register is above said predetermined upper limit and generating a negative digital output numerical value when the contents of said first storage register are below said predetermined lower limit;
• second storage register means having one input connected to said detector means and having at least one other input receiving clock pulses from said means for generating clock pulses;
• means for connecting the output of said detector means to said arithmetic unit also to said one input of said second storage register while maintaining the correct sign, whereby the content of said second storage register is the digital numerical value corresponding to the frequency of an input pulse sequence;
• means connecting said second storage register to said means for generating said clock pulse and for connecting the output of said second storage register to both said arithmetic unit and another input to said adder means whereby said digital numerical value in said second storage register is always subtracted from the content of said first storage register upon the occurrence of each clock pulse generated by said means for generating said clock pulse.