Analogue storage circuit including charge transfer device with compensation loop

An analogue storage circuit comprising:

• a multi-stage charge transfer device having an input whereby an analogue signal may be introduced into the device, an output, and means whereby an analogue signal introduced into the device may be shifted from said input, through successive stages of the device, to appear at said output, the magnitude of such an analogue signal appearing at said output being subject to an undesired variation;
• a quantising circuit arranged to quantise each signal applied thereto at a respective one of a plurality of substantially discrete levels in dependence upon the magnitude of the applied signal, the quantising circuit being connected between the output and the input of the charge transfer device to form a closed loop therewith;
• and
• means for introducing an analogue signal to be stored into said loop for circulation therearound;
• the separation of each pair of adjacent discrete levels being not less than 2.delta./K, where .+-..delta. is the magnitude of said undesired variation in analogue signals whose magnitude lies between that pair of levels and K is the gain factor of the charge transfer device for analogue signals whose magnitude lies between that pair of discrete levels;
• and
• the quantising circuit being arranged:
• (a) to quantise the analogue signal appearing at the output of the charge transfer device after the first passage of the analogue signal through the device either at one of the two adjacent discrete levels between which its magnitude lay prior to said first passage or, if the analogue signal is quantised at a discrete level prior to said first passage, at the same discrete level;
• and
• (b) to quantise the analogue signal, upon each subsequent receipt thereof, at the same one of said discrete levels.