Method of electrically isolating individual semiconductor circuits in a wafer
AssigneeNational Semiconductor Corporation
InventorsCarl T. Nelson, Brian E. Hollins
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AssigneeNational Semiconductor Corporation
InventorsCarl T. Nelson, Brian E. Hollins
Estimating the term…
A monolithic integrated circuit includes a vertical transistor having a low collector resistance with high current handling ability. The integrated circuit comprises a P type epitaxial layer grown on an N type substrate with both deep and shallow N type diffusions made into the P type layer. In the high current vertical transistor region with the deep N type diffusion, the deep diffusion penetrates the P layer to the N type substrate, whereas in the other transistor the shallow diffusion does not penetrate to the substrate. An N epitaxial layer is grown on the P type layer and thereafter normal processing techniques are used to form the base and emitter regions for the devices including the high current transistor which has its collector electrically coupled to the substrate.
In a method of electrically isolating individual semiconductor circuits in a wafer having a plurality of said semiconductor circuits formed therein, said wafer being of the type having first and second layers of a first conductivity type separated by an intervening third layer of a second conductivity type, said transistor circuits to be separated from each other and from the wafer into individual semiconductor chips by severing the wafer along intersecting boundary lines defining the boundaries of individual semiconductor circuit chips, the steps of:
Dependencies are inferred from the claim text.