Multiplex circuit with time delay for stabilization

A multiplex circuit for use with a plurality of measuring means which require a period of stabilization after activation, said circuit including a plurality of measuring stages, each stage having at least one measuring means, readout means and timing means, said timing means including first, second and third timers, said first and second timers having a common input with the output of said first timer being connected to a measuring means, the output of said second timer being connected to the input of said third timer, with the output of said third timer being connected to a readout means, the elapsed operating time of said first timer being equal to the sum of the operating times for said second and third timers, with said second timer activating said third timer a predetermined interval after turn-on of said first and second timers,

• said measuring stages being connected in cascade, with the timing means of one stage being connected to activate the timing means of the successive stage.