Negative R-S triggered latch
AssigneeGTE Automatic Electric Laboratories Incorporated
InventorGary W. Ester
Life of this patent
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Abstract
A negative, edge-triggered R-S latch, which provides predetermined output states for any and all R-S inputs, may be obtained by using an AND-OR-Invert (A-O-I) circuit in conjunction with a "D"-type flip-flop. The reset input and the Q-output of the flip-flop provide the inputs to one AND-gate of the A-O-I circuit. The set input and Q-output of the flip-flop provide the inputs to the other AND-gate. The output of the A-O-I provides the clock input to the flip-flop. The Q-output is also connected to the D-input of the flip-flop.
Claims6
A negative, edge-triggered R-S latch which provides predetermined outputs states for all R and S input conditions, said latch comprising:
- an R-input;
- an S-input;
- a Q-output;
- a Q-output;
- pulse logic means having an output and having only R, S, Q, an Q-inputs;
- said pulse logic means logically combining said inputs to provide a binary output depending upon the states of the inputs;
- and
- bistable means having as one input the Q-output and having as a second input the output of said pulse logic means, said bistable means being responsive only to the transitions between a first state and a second state of the binary output of said pulse logic means, said transitions changing the state of the Q and Q-outputs.
A negative, edge-triggered R-S latch which provides predetermined output states for all R and S input conditions, said latch comprising:
- a first AND-gate having two inputs and an output, one said input accepting the R-input;
- a second AND-gate having two inputs and an output, one said input accepting the S-input;
- a NOR-gate having two inputs and an output, one said input being connected to the output of said first AND-gate and the other said input being connected to the output of the second AND-gate;
- a D-type, edge-triggered flip-flop having Q and Q-outputs and having the clock input connected to the output of said NOR-gate, the D-input connected to the Q-output, said Q-output being connected to the other input of said first AND-gate and the Q-output also being connected to the other input of said second AND-gate.
Dependencies are inferred from the claim text.