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US 4,045,685 AGranted
MOS power stage for generating non-overlapping two-phase clock signals
AssigneeITT Industries, Inc.
InventorWilfried W. Gehrig
Life of this patent
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Abstract
This relates to an MOS power stage of a two-phase clock signal generator arranged on the same integrated circuit chip as the circuit to be driven. The generator consists of one MOSFET inverter, the output of which is multiplexed by the two clock signals. In this manner, power loss in the MOSFET is reduced.
Claims6
An MOS-power stage for generating non-overlapping two-phase clock signals from a first square wave signal having a pulse duty factor less than 0.5, comprising:
- a power inverter coupled to said square wave signals;
- first and second transistors each having a main current path coupled to the output of said power inverter;
- first and second capacitors, said first transistor having a gate coupled to its main current path via said first capacitor, and said second transistor having a gate coupled to its main current path via said second capacitor;
- and
- means for coupling the gate terminals of said first and second transistors to one of two inversely related auxiliary square wave signals, each having a pulse duty factor of 0.5 and a frequency equal to substantially half the frequency of said first square wave signal.
2 more elements
Dependencies are inferred from the claim text.