Information transfer bus circuit with signal loss compensation

An information transfer bus circuit for transferring data bits to a selected destination in response to a predetermined sequence of first and second clocking signals, the bus circuit comprising:

• a bus line having an associated first inherent capacitance storing a voltage representing a signal applied to the bus line;
• precharge means connected to the bus line and responsive to the second clocking signal, for precharging the bus line to a predetermined voltage level when the second clocking signal is activated;
• at least one data gating means connected to the bus line and arranged for receiving the first clocking signal and a selected data bit to be transferred to the selected destination, said data gating means being operative for discharging the precharged bus line when the first clocking signal is activated and the selected data bit is in a first logic state, said data gating means being further operative for maintaining the predetermined voltage level to which the bus line has been precharged when the first clocking signal is activated and the selected data bit is in a second logic state;
• at least one destination circuit connected to the bus line for receiving the selected data bit to be transferred, said destination circuit including a transfer gate connected to the bus line, the transfer gate being arranged for receiving the first clocking signal, the transfer gate including a second inherent capacitance storing the voltage representing the signal applied to the bus line in response to the first clocking signal;
• and
• a voltage enhancement capacitor connected to the bus line for coupling the first clocking signal to the bus line, said voltage enhancement capacitor being operative for enhancing the average high and low voltage levels within the destination circuit.